Performance Modelling and Dynamic Scheduling on Heterogeneous-ISA Multi-core Architectures

Abstract

Heterogeneous-ISA multi-core architectures have emerged as a promising design paradigm given the ever-increasing demands on single threaded performance. Such architectures comprise multiple cores that differ not just in micro-architectural parameters (e.g., fetch width, ROB size) but also in their Instruction Set Architectures (ISAs). These architectures extract previously latent performance gains by executing different phases of the program on the core (and ISA) best suited to it, as opposed to executing the entire program on a single ISA. In such a computing paradigm, maximum performance is only extracted when we ensure that at every point in the program’s execution, the program runs on the core best suited to it. In this work, we propose a migration framework that practically and accurately decides when to migrate the program across different cores (and ISAs) to extract maximum performance gains. Under the covers, this framework combines a regression based performance modelling technique with a greedy scheduling algorithm. Our performance modelling technique leverages hardware performance counters prevalent in all major processors today to accurately estimate the performance of the program on different ISAs to within an error of 6%. Putting it together with our greedy scheduler enables our framework to achieve single thread performance speedups of 29.6% with respect to a baseline single ISA heterogeneous architecture.