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LAST: An Efficient In-place Static Binary Translator for RISC Architectures

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Algorithms and Architectures for Parallel Processing (ICA3PP 2023)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 14488))

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Abstract

The lack of software has been a persistent issue for emerging instruction set architecture (ISA). To overcome this challenge, binary translation has emerged as a widely adopted solution, enabling programs written for older ISA to run on new ones. In the past, dynamic binary translation (DBT) was commonly utilized for software migration, but this technique required dynamic translation and often suffered from suboptimal efficiency. In contrast, Static binary translation (SBT) is an offline technique for translating binary code without runtime translation overhead. Existing SBT systems always employ address mapping tables to handle the address relocation problem, but this approach introduces performance overhead and leads to issues with indirect jump correctness. To address these limitations, we propose a novel static in-place instruction translation method for reduced-instruction set computing (RISC) architectures. This method ensures that the address of the guest program remains unchanged after translation, leveraging the regular length of various RISC instructions. We have implemented this method in a portable SBT tool called LAST, specifically designed to run MIPS or RISCV programs on the LoongArch platform. Based on the SPEC CPU2000 benchmark results, LAST achieves over 80% performance compared to the native LoongArch program, demonstrating its effectiveness and efficiency.

Supported by The National Key Research and Development Program of China under grant number 2022YFB3105103.

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Authors and Affiliations

  1. State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China

    Yanzhi Lan, Qi Hu, Gen Niu, Xinyu Li, Liangpu Wang & Fuxin Zhang

  2. University of Chinese Academy of Sciences, Beijing, China

    Yanzhi Lan, Qi Hu, Gen Niu, Xinyu Li, Liangpu Wang & Fuxin Zhang

Authors
  1. Yanzhi Lan
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  2. Qi Hu
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  3. Gen Niu
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  4. Xinyu Li
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  5. Liangpu Wang
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  6. Fuxin Zhang
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Correspondence to Fuxin Zhang .

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Editors and Affiliations

  1. Royal Melbourne Institute of Technology, Melbourne, VIC, Australia

    Zahir Tari

  2. Tianjin University, Tianjin, China

    Keqiu Li

  3. University of Arizona, Tucson, AZ, USA

    Hongyi Wu

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Lan, Y., Hu, Q., Niu, G., Li, X., Wang, L., Zhang, F. (2024). LAST: An Efficient In-place Static Binary Translator for RISC Architectures. In: Tari, Z., Li, K., Wu, H. (eds) Algorithms and Architectures for Parallel Processing. ICA3PP 2023. Lecture Notes in Computer Science, vol 14488. Springer, Singapore. https://doi.org/10.1007/978-981-97-0801-7_14

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  • DOI: https://doi.org/10.1007/978-981-97-0801-7_14

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  • Online ISBN: 978-981-97-0801-7

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