Abstract
Reconfigurable architecture has great potential in computation-intensive and memory-intensive applications due to its flexible information configuration. Aiming at the problem of low computing efficiency caused by the inconsistency between different granularity data and the underlying hardware structure in applications such as communication baseband signal processing, a parallel computing method supporting multi-bit data is proposed, and a dynamic granularity configuration structure used this method is designed based on reconfigurable array processors. The structure divides the calculation granularity into 8 bits, 16 bits, and 32 bits, and realizes four functions: data-combination, data-splitting, parallel-addition, and parallel-multiplication. These features increase the parallelism and flexibility of array structures. The experimental results show that the speedup ratio can reach 1.5 within a certain error range, the running time is reduced by about 20%, and the code complexity is also significantly reduced. In addition, the maximum operating frequency of the dynamic configuration circuit is 133.5 MHz by FPGA comprehensive implementation, which can realize the dynamic configuration of different granularity data in the calculation and achieve parallel computing of multi-bit data.
Supported by National Key R &D Program of China
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This work was supported by National Key R &D Program of China (2022ZD0119001); Key projects of National Natural Science Foundation of China (61834005).
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Jiang, L., Liu, S., Zhu, J., Shan, R., Li, Y. (2024). Dynamic Multi-bit Parallel Computing Method Based on Reconfigurable Structure. In: Tari, Z., Li, K., Wu, H. (eds) Algorithms and Architectures for Parallel Processing. ICA3PP 2023. Lecture Notes in Computer Science, vol 14488. Springer, Singapore. https://doi.org/10.1007/978-981-97-0801-7_20
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