Abstract
The tight integration of hardware and software enables very long instruction word (VLIW) architectures to vastly outperform superscalar architectures in performance. The performance of VLIW architectures largely depends on the careful design of their instruction sets. The design of VLIW instruction sets is an iterative process. In the instruction format design phase, issues such as encoding inefficiency, format adjustment, and decoding complexity may arise. In the evaluation and verification phase of the instruction set, the challenge of rapid modeling of iterative instruction set architectures (ISA) may emerge. To address the aforementioned issues, we propose an architecture description language. By automatically generating instruction formats, it solves problems such as encoding inefficiency, format adjustment, and decoding complexity. By generating encoding schemes, it provides an interface to solve the problem of rapid modeling of iterative ISA. This paper delineates this technology and evaluates it on the MT-3000 ISA. The experimental results demonstrate that it can automatically and expeditiously generate encoding schemes and optimize the issues in instruction format design. This can effectively accelerate the progress of the instruction set.
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Acknowledgment
This work is supported by NUDT Research Project (No. 23-ZZCX-JDZ-11), PDL Research Project (No. 2021-KJWPDL-11), Key Laboratory of Advanced Microprocessor Chips and Systems.
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Xiao, X., Liu, Z. (2024). An Adaptive Instruction Set Encoding Automatic Generation Method for VLIW. In: Tari, Z., Li, K., Wu, H. (eds) Algorithms and Architectures for Parallel Processing. ICA3PP 2023. Lecture Notes in Computer Science, vol 14487. Springer, Singapore. https://doi.org/10.1007/978-981-97-0834-5_17
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DOI: https://doi.org/10.1007/978-981-97-0834-5_17
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