Abstract
With Moore’s Law slowing down, the development of SoCs has encountered a bottleneck. Integrating more functional units and larger on-chip storage leads to a dramatic increase in chip area, resulting in lower chip yields and higher costs. Most researches and industry products began to seek to use advanced connection and packaging technologies to decompose the raw chip into multiple smaller, higher yield, and more cost-effective chiplets, and then packet them. Interposer-based 2.5D integration, as an emerging packaging technology, is widely used in chiplet-based systems. However, even if both the interposer and chiplets are deadlock-free, deadlock dependency cycles across them may still occur after integration. To address these problems, this paper proposes a deadlock resolution called Absorb for 2.5D integrated chiplet systems, which is different from deadlock avoidance and deadlock recovery. By regularly absorbing inter-chiplet packets, global deadlock freedom is achieved, and no extra VCs are for deadlock resolution. Our proposed Absorb maintains the modularity of each chiplet and imposes no restrictions on the routing algorithm. Our evaluations show that compared with the previously proposed deadlock-free designs in 2.5D-chiplet systems, Absorb provides an average performance improvement of about 7.5%, and the area overhead is less than 6%.
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Yang, Y., Li, T., Dai, Y., Wang, B., Ma, S., Sun, Y. (2024). Absorb: Deadlock Resolution for 2.5D Modular Chiplet Based Systems. In: Tari, Z., Li, K., Wu, H. (eds) Algorithms and Architectures for Parallel Processing. ICA3PP 2023. Lecture Notes in Computer Science, vol 14487. Springer, Singapore. https://doi.org/10.1007/978-981-97-0834-5_27
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DOI: https://doi.org/10.1007/978-981-97-0834-5_27
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