Abstract
Large-scale computation and data processing are common tasks in machine learning. While traditional central processors are capable of performing these tasks, their computational speed is often inadequate when dealing with large-scale data sets and deep neural networks. As a result, many accelerators have emerged, such as graphics processors, field-programmable gate arrays, etc. FPGA have become a widely used type of accelerator compared to other accelerators due to their high flexibility, high performance, low power consumption, and low latency. However, most of the existing FPGA accelerators only accelerate single modules of CNN, RNN, and attention modules, and few cases of joint acceleration for different types of network combinations are mentioned. Therefore, this work is based on the hardware design of a model with a combination of convolutional and attention modules, and the way they combine to process the data is a perfect fit for the core of hardware acceleration. On the hardware device, the data in this model can flow into the computation at the same time to obtain parallel processing speed. We use a cut that is more suitable for hardware parallelism to process the data coming into both modules, thus making the best use of resources and keeping the time of both modules close to each other. In the same way, for the most computationally heavy loop structure, we have adapted the array structure for faster computation. We also parallelize the design of the serial linear layer in the attention module after the efforts in this paper, the model is further streamlined and accelerated, and finally, our model achieves a speedup of 12.5 times with only a 0.25 decrease in BLEU.
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References
Vaswani, A., et al.: Attention is all you need. arXiv (2017)
Hassani, A., Walton, S., Shah, N., Abuduweili, A., Li, J., Shi, H.: Escaping the big data paradigm with compact transformers. arXiv preprint arXiv:2104.05704 (2021)
d’Ascoli, S., Touvron, H., Leavitt, M.L., Morcos, A.S., Biroli, G., Sagun, L.: ConViT: improving vision transformers with soft convolutional inductive biases. In: International Conference on Machine Learning, pp. 2286–2296. PMLR (2021)
Mehta, S., Rastegari, M.: MobilEViT: light-weight, general-purpose, and mobile-friendly vision transformer. arXiv preprint arXiv:2110.02178, 2021
Wu, Z., Liu, Z., Lin, J., Lin, Y., Han, S.: Lite transformer with long-short range attention. arXiv preprint arXiv:2004.11886 (2020)
Chen, Y., Dai, X., Liu, M., Chen, D., Yuan, L., Liu, Z.: Dynamic convolution: attention over convolution kernels. In: Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, pp. 11030–11039 (2020)
Xu, D., Chen, Y., Cui, N., Li, J.: Towards multi-dimensional knowledge-aware approach for effective community detection in LBSN. In: World Wide Web, pp. 1–24 (2022)
Shi, R., et al.: FTDL: a tailored FPGA-overlay for deep learning with high scalability. In: 2020 57th ACM/IEEE Design Automation Conference (DAC), pp. 1–6. IEEE (2020)
Yang, Y., et al.: Synetgy: algorithm-hardware co-design for convnet accelerators on embedded FPGAs. In: Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pp. 23–32 (2019)
Ma, N., Zhang, X., Zheng, H.T., Sun, J.: ShuffleNet V2: practical guidelines for efficient CNN architecture design. In: Proceedings of the European Conference on Computer Vision (ECCV), pp. 116–131 (2018)
Park, J., Yoon, H., Ahn, D., Choi, J., Kim, J.-J.: Optimus: Optimized matrix multiplication structure for transformer neural network accelerator. Proc. Mach. Learn. Syst. 2, 363–378 (2020)
Song, H., Mao, H., Dally, W.J.: Deep compression: compressing deep neural networks with pruning, trained quantization and huffman coding. In: ICLR (2016)
Chen, Y., Zhang, N., Yan, J., Zhu, G., Min, G.: Optimization of maintenance personnel dispatching strategy in smart grid. World Wide Web 26(1), 139–162 (2023)
Zhang, C., Li, P., Sun, G., Guan, Y., Cong, J.: Optimizing FPGA-based accelerator design for deep convolutional neural networks. In: The 2015 ACM/SIGDA International Symposium (2015)
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Hu, W., Zhong, Z., Liu, F., Li, H. (2024). FBCA: FPGA-Based Balanced Convolutional Attention Module. In: Song, X., Feng, R., Chen, Y., Li, J., Min, G. (eds) Web and Big Data. APWeb-WAIM 2023. Lecture Notes in Computer Science, vol 14333. Springer, Singapore. https://doi.org/10.1007/978-981-97-2387-4_23
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DOI: https://doi.org/10.1007/978-981-97-2387-4_23
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