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Performance Augmentation of DIMOS Transistor

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Intelligent Data Engineering and Analytics (FICTA 2023)

Part of the book series: Smart Innovation, Systems and Technologies ((SIST,volume 371))

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Abstract

In this study, the source region of a partially depleted PD SOI n-MOSFET has a high peak-to-valley ratio tunnel diode buried within it. In the MOSFET source region, intrinsic germanium is added at various micro-lengths. The result is compared with various embedded tunnel diode peak-to-valley ratios to determine the constant saturation drain current with a large voltage swing. Other phenomena that come from this device, such as low output resistance, capacitance, high voltage gain, and output signal distortion, were greatly reduced. The proposed device is one of the most promising candidates for low-power digital and analog circuits. This structure’s performance is evaluated using I–V characteristics for various voltages using the COGENDA device simulator.

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Authors and Affiliations

  1. Department of IoT, School of Computer Science and Engineering, Vellore Institute of Technology, Vellore, Tamilnadu, 632 014, India

    S. Jafar Ali Ibrahim

  2. Department of ECE, QIS College of Engineering and Technology, Ongole, Andhra Pradesh, India

    V. Jeya Kumar & M. Mani Deepika

  3. School of Computer Science and Engineering, QIS College of Engineering and Technology, Ongole, Andhra Pradesh, India

    N. S. Kalyan Chakravarthy

  4. CFY Deanship, King Saud University, Riyadh, Saudi Arabia

    Alhaf Malik Kaja Mohideen

  5. Department of Information Technology, Nadar Saraswathi College of Engineering and Technology, Theni, Tamilnadu, India

    M. Sathya

Authors
  1. S. Jafar Ali Ibrahim
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  2. V. Jeya Kumar
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  3. N. S. Kalyan Chakravarthy
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  4. Alhaf Malik Kaja Mohideen
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  5. M. Mani Deepika
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  6. M. Sathya
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Corresponding author

Correspondence to S. Jafar Ali Ibrahim .

Editor information

Editors and Affiliations

  1. Department of Electronics Engineering, Faculty of Engineering and Technology (UNSIET), Veer Bahadur Singh Purvanchal University, Jaunpur, Uttar Pradesh, India

    Vikrant Bhateja

  2. Cardiff School of Technologies, Cardiff Metropolitan University, Cardiff, Warwickshire, UK

    Fiona Carroll

  3. Faculty of Engineering, University of Porto, Porto, Portugal

    João Manuel R. S. Tavares

  4. Cardiff Metropolitan University, Cardiff, Warwickshire, UK

    Sandeep Singh Sengar

  5. Faculty of Computer and Information Science, University of Ljubljana, Ljubljana, Slovenia

    Peter Peer

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© 2023 The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.

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Ibrahim, S.J.A., Kumar, V.J., Chakravarthy, N.S.K., Mohideen, A.M.K., Deepika, M.M., Sathya, M. (2023). Performance Augmentation of DIMOS Transistor. In: Bhateja, V., Carroll, F., Tavares, J.M.R.S., Sengar, S.S., Peer, P. (eds) Intelligent Data Engineering and Analytics. FICTA 2023. Smart Innovation, Systems and Technologies, vol 371. Springer, Singapore. https://doi.org/10.1007/978-981-99-6706-3_51

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