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MFHBT: Hybrid Binary Translation System with Multi-stage Feedback Powered by LLVM

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Advanced Parallel Processing Technologies (APPT 2023)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 14103))

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Abstract

The shortage of applications has become a major concern for new Instruction Set Architecture (ISA). Binary translation is a common solution to overcome this challenge. However, the performance of binary translation is heavily dependent on the quality of the translated code. To achieve high-quality translation, recent studies focus on integrating binary translators with compilation optimization methods. Nevertheless, such integration faces two main challenges. Firstly, it is hard to employ complex compilation optimization techniques in a dynamic binary translator (DBT) without introducing significant runtime overhead. Secondly, the task of implementing register mapping in the compiler is challenging, which can reduce expensive memory access instructions generated to maintain the guest CPU state. To resolve these challenges, we propose a hybrid binary translation system with multi-stage feedback, combining dynamic and static binary translator, named MFHBT. This system eliminates the runtime overhead caused by compilation optimization. Additionally, we introduce a mechanism to implement the register mapping through inline constraints and stack variables in the compiler. We implement a prototype of this new system powered by LLVM. Experimental results demonstrate an 81% decrease in the number of memory access instructions and a performance improvement of 3.28 times compared to QEMU.

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Notes

  1. 1.

    The EFLAGS register is the status register that contains the current state of a x86 CPU.

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Acknowledgment

We would like to thank all the anonymous reviewers for their helpful comments and suggestions. This project is funded by the 2022 National Key Research and Development Program “Security Protection Technology for Distribution Network Key Information Infrastructure” Project 3 Distribution Network Computing Equipment Security Enhancement Technology Research and Localization Development (Project No. 2022YFB3105103).

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Authors and Affiliations

  1. SKLP, Institute of Computing Technology, CAS, Beijing, China

    Zhaoxin Yang, Xuehai Chen, Liangpu Wang & Fuxin Zhang

  2. University of Chinese Academy of Sciences, Beijing, China

    Zhaoxin Yang, Xuehai Chen, Liangpu Wang & Fuxin Zhang

  3. University of Science and Technology of China, Hefei, China

    Weiming Guo & Dongru Zhao

  4. State Grid Liaoning Electric Power Supply Co. Ltd., Shenyang, China

    Chao Yang

Authors
  1. Zhaoxin Yang
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  2. Xuehai Chen
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  3. Liangpu Wang
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  4. Weiming Guo
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  5. Dongru Zhao
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  6. Chao Yang
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  7. Fuxin Zhang
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Corresponding author

Correspondence to Fuxin Zhang .

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Editors and Affiliations

  1. Shanghai Jiao Tong University, Shanghai, China

    Chao Li

  2. Tsinghua University, Beijing, Beijing, China

    Zhenhua Li

  3. National University of Defense Technology, Nanjing, China

    Li Shen

  4. Shanghai Jiao Tong University, Shanghai, China

    Fan Wu

  5. Nankai University, Tianjin, China

    Xiaoli Gong

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© 2024 The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.

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Yang, Z. et al. (2024). MFHBT: Hybrid Binary Translation System with Multi-stage Feedback Powered by LLVM. In: Li, C., Li, Z., Shen, L., Wu, F., Gong, X. (eds) Advanced Parallel Processing Technologies. APPT 2023. Lecture Notes in Computer Science, vol 14103. Springer, Singapore. https://doi.org/10.1007/978-981-99-7872-4_18

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  • DOI: https://doi.org/10.1007/978-981-99-7872-4_18

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  • Publisher Name: Springer, Singapore

  • Print ISBN: 978-981-99-7871-7

  • Online ISBN: 978-981-99-7872-4

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