Design of Low-Power and Area-Efficient Square Root Carry Select Adder Using Binary to Excess-1 Converter (BEC)

Abstract

The Carry Select Adder (CSLA) is commonly used in VLSI design applications like data-processing processors, ALUs, and microprocessors to perform fast arithmetic operations. Compared to primitive designs like Ripple Carry Adder and Carry Look Ahead Adder, the regular CSLA offers optimized results in terms of area. However, it is still possible to reduce the area and power consumption of CSLA by implementing a simpler and more efficient gate-level modification. In this work, all the CSLA structures were designed using Verilog HDL while pre-layout simulation and synthesis were done using Quartus Prime, ModelSim and Synopsys EDA tools. The final results analysis obtained have proven that the BEC-based SQRT CSLA is better than regular square root CSLA (SQRT CSLA) as it has reduced total cell area by 19.54 (16-bit) and 19.44% (32-bit) as well as reduced total dynamic power by 8.52 (16-bit) and 8.75% (32-bit). Ultimately, the modified SQRT CSLA structure using BEC method showed significant lower dynamic power consumption and smaller cell area than the regular SQRT CSLA.