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Guaranteed fault detection sequences for single transition faults in finite state machine models using concurrent fault simulation

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Abstract

This paper presents a new algorithm for the generation of test sequences for finite state machines. Test sequence generation is based on the transition fault model, and the generation of state-pair distinguishing sequences. We show that the use of state-pair distinguishing sequences generated from a fault-free finite state machine will remain a distinguishing sequence even in the presence of a single transition fault, thus guaranteeing complete single transition fault coverage. Analysis and experimental results show that the complexity of the test sequence generation algorithm is less than those of the previous algorithms. The utility of the transition fault model, and the generated test sequences is shown by their application to sequential logic circuits. These results show more than a factor of 10 improvement in the test generation time and some reduction in test length while maintaining 100% transition fault coverage.

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References

  1. T.S. Chow, “Testing Software Design Modeled by Finite State Machines,” IEEE Transactions on Software Engineering, Vol. SE-4, pp. 178–187, Mar. 1978.

    Google Scholar 

  2. A.V. Aho, R. Sethi, and J.D. Ullman, Compilers: Principles, Techniques, and Tools, Addison-Wesley, Reading, MA, 1986.

    Google Scholar 

  3. G.J. Holzmann, Design and Validation of Computer Protocols, Prentice-Hall, Englewood Cliffs, NJ, 1991.

    Google Scholar 

  4. E.F. Moore, “Gedanken-Experiments on Sequential Machines,” in Automata Studies (Annals of Mathematics Studies), pp. 129–153, 1956.

  5. F.C. Hennie, “Fault-Detecting Experiments for Sequential Circuits,” in Proc. 5th Annual Symposium on Switching Circuit Theory and Logical Design, 1964, pp. 95–110.

  6. E.P. Hsieh, “Checking Experiments for Sequential Machines,” IEEE Transactions on Computers, Vol. C-20, pp. 1152–1166, Oct. 1971.

    Google Scholar 

  7. K. Sabnani and A. Dahbura, “A Protocol Test Generation Procedure,” Computer Networks, Vol. 15, pp. 285–297, 1988.

    Google Scholar 

  8. K.-T. Cheng and V.D. Agrawal, “A Partial Scan Method for Sequential Circuits with Feedback,” IEEE Transactions on Computers, Vol. 39–4, pp. 544–548, Apr. 1990.

    Google Scholar 

  9. W.T. Cheng, “The BACK Algorithm for Sequential Test Generation,” in Proc. International Conference on Computer Design (ICCD), 1988, pp. 66–69.

  10. A. Ghosh, S. Devadas, and A.R. Newton, “Test Generation for Highly Sequential Circuits,” in Proc. International Conference on Computer-Aided Design (ICCAD), 1989, pp. 362–365.

  11. H.-K.T. Ma, S. Devadas, A.R. Newton, and A.S. Vincentelli, “Test Generation for Sequential Circuits,” IEEE Transactions on CAD, Vol. 7, No. 10, pp. 1081–1093, Oct. 1988.

    Google Scholar 

  12. M.J. Bending, “HITEST—A Knowledge-Based Test Generation System,” IEEE Designand Test of Computers, Vol. 1, pp. 83–93, May 1984.

    Google Scholar 

  13. K.-T. Cheng and V.D. Agrawal, “Design of Sequential Machines for Efficient Test Generation,” in Proc. International Conference on Computer-Aided Design (ICCAD), 1989, pp. 358–361.

  14. K.T. Cheng and J.Y. Jou, “Functional Test Generation for Finite State Machines,” in Proc. International Test Conference (ITC), 1990, pp. 162–168.

  15. I. Pomeranz and S.M. Reddy, “On Achieving a Complete Fault Coverage for Sequential Machines using the Transition Fault Model,” in Proc. Design Automation Conference (DAC), 1991, pp. 341–346.

  16. I. Pomeranz and S.M. Reddy, “Test Generation for Synchronous Sequential Circuits using Multiple Observation Times,” in Proc. Fault-Tolerant Computing Symposium, 1991, pp. 52–59.

  17. K.-T. Cheng and J.-Y. Jou, “A Functional Fault Model for Sequential Machines,” IEEE Transactions on CAD, Vol. 11, No. 9, pp. 1065–1073, Sept. 1992.

    Google Scholar 

  18. N.L. Cooray, Efficient Fault Modeling and Test Generation for Finite State Machines at the Functional Abstraction Level, Master's Thesis, Northeastern University, Department of Electrical and Computer Engineering, Aug. 1993.

  19. M. Karam and G. Saucier, “Functional versus Random Test Generation for Sequential Circuits,” Jour. Electronic Testing: Theory and Applications (JETTA), Vol. 4, pp. 33–41, Feb. 1993.

    Google Scholar 

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Authors and Affiliations

  1. Electrical and Computer Engineering Department, Northeastern University, 02115, Boston, MA, USA

    Niranjan L. Cooray & Edward W. Czeck

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  1. Niranjan L. Cooray
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  2. Edward W. Czeck
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Now with Intel Corporation, FM5-161, 1900 Prairie City Road, Folsom, CA 95630.

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Cooray, N.L., Czeck, E.W. Guaranteed fault detection sequences for single transition faults in finite state machine models using concurrent fault simulation. J Electron Test 8, 261–273 (1996). https://doi.org/10.1007/BF00133388

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  • DOI: https://doi.org/10.1007/BF00133388

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