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ITA: An algorithm for I DDQ testability analysis

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Abstract

This paper presents the I DDQ Testability Analysis (ITA) algorithm for the estimation of a circuit design's leakage fault testability. The algorithm is based on the calculation of the probability of applying each of a set of “essential vectors” to each gate in the circuit. The essential vectors for each gate represent the minimal vector set that provides maximal leakage fault coverage.

ITA assumes independence of circuit net values, except in the case of reconvergent fanout. Reconvergent fanout is identified by “levelizing” the circuit and propagating sets of labels from the primary inputs forward through the circuit, beginning with unique labels (integers) on each primary input. ITA evaluation of reconvergent fanout points then uses a backward implication procedure to calculate the essential vector probability values for the reconvergent gate, except in the case where backward implication is not deterministic.

Results of an implementation of ITA are presented for a set of benchmark circuits, including a sample of the ISCAS '85 and '89 circuits.

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Authors and Affiliations

  1. Center for Digital Systems Engineering, Research Triangle Institute, P.O. Box 12194, 27709-2194, RTP, NC, USA

    Michael G. McNamer

  2. Dept. of Electrical and Computer Engineering, North Carolina State University, 27695-7911, Raleigh, NC, USA

    H. Troy Nagle

Authors
  1. Michael G. McNamer
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  2. H. Troy Nagle
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McNamer, M.G., Nagle, H.T. ITA: An algorithm for I DDQ testability analysis. J Electron Test 8, 287–298 (1996). https://doi.org/10.1007/BF00133390

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  • DOI: https://doi.org/10.1007/BF00133390

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