Skip to main content
SpringerLink
Log in

Fault simulation using small fault samples

  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

This article emphasizes simulation-based sampling techniques for estimating fault coverage that use small fault samples. Although random testing is considered to be the primary area of application of the technique it is also suitable for estimating the fault coverage of nonrandom tests based on specific fault models. Especially for fault coverages exceeding 95%, it is shown that a precise estimate can be obtained using a fault sample of only 500 faults. The estimation is based on a binomial approximation of the probability density of the sample fault coverage. Using Bayes statistics an estimate is obtained whose accuracy is a linear function of the sample size if the fault coverage approaches 100%. The sample size is independent of the circuit size, thus making fault sampling particularly interesting for the fault simulation of ULSI designs due to the resulting reduction of the time complexity of fault simulation from O(N 2) to O(N).

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. P.H. Bardell, W.H. McAnney, and J. Savir, “Built-In Test for VLSI—Pseudorandom Techniques,” Wiley, 1987.

  2. K.J. Antreich and M.H. Schulz, “Fast Fault Simulation in Combinational Circuits,” Proc. Intern. Conf. Comput.-Aid. Design, 1986.

  3. L. Carter, B.K. Rosen, and J.D. Rutledge, “HSS—A High Speed Simulator,” IBM Research Report, RC 11738, pp. 1–34, 1986.

  4. W.-T. Chen and J.H. Patel, “PROOFS: A Super Fast Fault Simulator for Sequential Circuits,” Proc. Europ. Design Automat. Conf., Glasgow, Scotland, 12–15 March pp. 475–479, 1990.

  5. W. Daehn and M. Geilert, “Fast Fault Simulation by Compiler Driven Single Fault Propagation,” Proc. Intern. Test Conf., Washington, Sept. 1–3, pp. 286–292, 1987.

  6. S. Köppe and C.W. Starke, “Logiksimulation komplexer Schaltungen für sehr groβe Testlängen,” Vorträge der NTG-Fachtagung “Groβintegration,” Baden-Baden, pp. 73–80, 1985.

  7. J.A. Waicukauski and E. Lindblom, “Transition Fault Simulation by Parallel Pattern Single Fault Propagation,” Proc. Intern. Test Conf., Washington, pp. 542–549, 1986.

  8. M.A. Breuer and A.D. Friedman, Diagnosis & Reliable Design of Computers, Computer Science Press, Woodlands Hills, CA 1976.

    Google Scholar 

  9. Z. Barzilai and B.K. Rosen, “Comparison of AC Self-Testing Procedures,” Proc. Intern. Test Conf., Washington, pp. 89–94, 1983.

  10. W. Daehn and D. Kannemacher, “Ein selbsttestenden CMOS-Rechenwerk,” GMD Studie 110, 2. E.I.S.-Workshop, Bonn, 3. pp. 227–233, 1986.

  11. V. Iyengar, B.K. Rosen, and I. Spillinger, “Delay Test Generation 1 - Concepts and Coverage Metrics,” Proc. Intern. Test Conf., Washington, pp. 857–875, 1988.

  12. S. Köppe, “Modelling and Simulation of Delay Faults in CMOS Logic Circuits,” Proc. Intern. Test Conf., Washington, pp. 530–536, 1986.

  13. F. Fink, M.H. Schulz, and K. Fuchs, “Parallel Pattern Fault Simulation of Path Delay Faults,” Proc. 26th Design Autom. Conf., Las Vegas, 1989.

  14. M.H. Doshi, R.B. Sullivan, and D.M. Schuler, “Themis Logic Simulator—A Mix Mode, Multi Level, Hierarchical, Interactive Digital Circuit Simulator,” Proc. 21st Design Autom. Conf., pp. 24–31, 1984.

  15. S. Gai, F. Somenzi, and E. Ulrich, “Advanced Techniques for Concurrent Multilevel Simulation,” Proc. Intern. Conf. Comput.-Aid. Design, pp. 334–337, 1986.

  16. A. Motohara, M. Murakami, M. Urano, Y. Masuda, and M. Sugano, “An Approach to Fast Hierarchical Fault Simulation,” Proc. 25th Design Autom. Conf., pp. 698–703, 1988.

  17. W.A. Rogers and J.A. Abrahams, “CHIEFS: A Concurrent Hierarchical and Extensible Fault Simulator,” Proc. Intern. Test Conf., Philadelphia, pp. 710–716, 1985.

  18. W.A. Rogers, J.A. Abrahams, R.K. Roy, and P.A. Duba, “Fault Simulation in a Distributed Environment,” Proc. 25th Design Autom. Conf., pp. 686–691, 1988.

  19. S.K. Jain and V.D. Agrawal, “STAFAN: An Alternative to Fault Simulation,” Proc. 21st Design Autom. Conf., pp. 18–23, 1984.

  20. H.J. Wunderlich, “PROTEST: A Tool for Probabilistic Testability Analysis,” Proc. 22nd Design Autom. Conf., pp. 204–211, 1985.

  21. G.R. Case, “A Statistical Method for Test Sequence Evaluation,” Proc. 12th Design Autom. Conf., Boston, June, pp. 257–260, 1975.

  22. A Wald, “Sequential Analysis,” Wiley, New York, 1947.

    Google Scholar 

  23. V.D. Agrawal, “Sampling Techniques for Determining Fault Coverage in LSI Circuits,” J. Digital Syst. 5(3):189–201, 1981.

    Google Scholar 

  24. C.R. Rao, “Information and Accuracy Obtainable in an Estimation of a Statistical Parameter,” Bulletin Calcutta Mathematical Society 37:45, 1945.

    Google Scholar 

  25. H. Cramér, “Mathematical Methods in Statistics,” Princeton University Press, Princeton, 1946.

    Google Scholar 

  26. J. Savir and P.H. Bardell, “On RAndom Pattern Test Length,” IEEE Trans. Comput. C-33(6):467–474, 1984.

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. SICAN GmbH, Hannover, Germany

    Wilfried Daehn

Authors
  1. Wilfried Daehn
    View author publications

    You can also search for this author in PubMed Google Scholar

Additional information

This work was performed while Dr. Daehn was with the Laboratorium fuer Informationstechnologie at the university of Han- nover, Germany.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Daehn, W. Fault simulation using small fault samples. J Electron Test 2, 191–203 (1991). https://doi.org/10.1007/BF00133503

Download citation

  • Received:

  • Revised:

  • Issue Date:

  • DOI: https://doi.org/10.1007/BF00133503

Keywords

Search

Navigation