Abstract
In this article, yield enhancement and manufacturing throughput of large repairable memories are analyzed. These objectives are met by repairability/unrepairability detection. Initially two new techniques for detection of memory chips with redundancy are presented. Initially, a heuristic, yet efficient approach is proposed. This first approach is based on finding a very good approximation to the minimum covering set. An algorithm, which executes in quadratic time with respect to the largest dimension of the memory, is presented. This algorithm is executed off-line, that is, when the memory has been fully diagnosed. New conditions for detection are presented and fully analyzed. These are based on a more accurate estimation of the regions of repairability and unrepairability. Hence, this results in a reduction of the uncertainty region, where the status of a memory cannot be established without executing a fully exhaustive search algorithm. The second approach to repairability/unrepairability detection is based on a more complex covering relationship, namely the generalized leading element. A model for manufacturing throughput of large repairable memories is presented.
A new repair algorithm which utilizes a ternary tree approach, is also presented. This repair algorithm is perfect in the sense that it finds the optimal repair-solution (whenever one exists) after the memory has not been diagnosed unrepairable.
Illustrative examples and simulation results show that considerable improvements for average and the worst-case analysis over existing techniques can be achieved.
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This research was supported in part by grants from AT&T and NATO.
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Shen, YN., Lombardi, F. Yield enhancement and manufacturing throughput of redundant memories by repairability/unrepairability detection. J Electron Test 1, 43–57 (1990). https://doi.org/10.1007/BF00134014
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DOI: https://doi.org/10.1007/BF00134014