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Initialization issues in asynchronous circuit synthesis

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Abstract

A design specification is said to be functionally uninitializable if an initializable implementation cannot be obtained. Due to the absence of any initialization sequence, a fault simulator or test generator that assumes an unknown starting state will be completely ineffective for uninitializable circuits. We present a novel procedure for synthesizing initializable asynchronous circuits from functionally uninitializable Signal Transition Graphs (STG). After characterizing the necessary conditions for functional uninitializability, we propose a technique that transforms the original STG into an equivalent, functionally initializable STG. We show that the presence of concurrency provides the designer with an extra degree of flexibility when implementing the circuit. It is shown that initializability can be achieved by sacrificing minimal concurrency and without violating the syntactic properties of the STG required for a hazard-free implementation. The synthesis of a trigger module illustrates this procedure.

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References

  1. A. Marshall, B. Coates, and P. Siegel “Designing an Asynchronous Communications Chip,” IEEE Design & Test of Computers, Vol. 11, No. 2, pp. 8–21, Sept. 1994.

    Google Scholar 

  2. K. van Berkel, R. Burgess, J. Kessels, M. Roncken, F. Schalij, and A. Peeters “Asynchronous Circuits for Low Power: A DCC Error Corrector,” IEEE Design & Test of Computers, Vol. 11, No. 2, pp. 22–32, Sept. 1994.

    Google Scholar 

  3. J. Tierno, A. Martin, D. Borkovic, and T. Lee “A 100-MIPS GaAs Asynchronous Microprocessor,” IEEE Design & Test of Computers, Vol. 11, No. 2, pp. 43–49, Sept. 1994.

    Google Scholar 

  4. T.A. Chu, Synthesis of Self-Timed VLSI Circuits from GraphTheoretical Specifications, Ph.D. Thesis, MIT, 1987.

  5. S. Hauck, “Asynchronous Design Methodologies: An Overview,” Technical Report TR 93-05-07, University of Washington, Dept. of CS&E, 1993.

  6. T.H.Y. Meng, Synchronization Design for Digital Systems, Kluwer Academic Publishers, Boston, MA, 1991.

    Google Scholar 

  7. S.T. Chakradhar, S. Banerjee, R.K. Roy, and D.K. Pradhan, “Synthesis of Initializable Asynchronous Circuits,” Proc. of the 7th Intl. Conf. on VLSI Design, Jan. 1994, pp. 383–388.

  8. M. Abramovici, M. Breuer, and A. Friedman, Digital Systems Testing and Testable Design, Computer Science Press, New York, NY, 1990.

    Google Scholar 

  9. N. Hamida, B. Kaminska, and Y. Savaria, Initializability, “A Measure for Sequential Test,” Proc. of the Int'l Symp. on Circuits and Systems, 1993, pp. 1619–1622.

  10. C. Pixley, S.-W. Jeong, and G.D. Hatchel, “Exact Calculation of Synchronization Sequences Based on Binary Decision Diagrams,” Proc. of the 29th ACM/IEEE Design Automation Conference, 1992, pp. 620–623.

  11. K.T. Cheng and V.D. Agrawal, “State Assignment for Initializable Synthesis,” Proc. of the Int. Conf. on Computer-Aided Design, 1989, pp. 212–215.

  12. B. Mathew and D.G. Saab “Partial Reset: An Inexpensive Design for Testability Approach,” Proc. of the EDAC/EURO-ASIC, April 1993, pp. 151–155.

  13. S. Banerjee, R.K. Roy, S.T. Chakradhar, and D.K. Pradhan, “Signal Transition Graph Transformations for Initializability,” Proc. of the EDAC/EURO-ASIC, April 1994.

  14. S. Banerjee, R.K. Roy, S.T. Chakradhar, and D.K. Pradhan, “Initialization Issues in the Synthesis of Asynchronous Circuits,” Proc. of the Intl. Conf. on Computer Design, Oct. 1994, pp. 447–452.

  15. C. Ykman-Couvreur, P. Vanbekbergen, and B. Lin, “Concurrency Reduction Transformations on State Graphs for Asynchronous Circuits,” Proc. of the Intl. Workshop on Logic Synthesis, May 1993, pp. 1a-1–1a-13.

  16. S.H. Unger, Asynchronous Sequential Switching Circuits, Wiley Interscience, New York, 1969.

    Google Scholar 

  17. R.E. Miller, Switching Theory, Wiley and Sons, Vol. 2, 1965.

  18. T.A. Chu “On the Models for Designing VLSI Asynchronous Digital Systems,” INTEGRATION, The VLSI Journal, Vol. 4, pp. 99–113, 1986.

    Google Scholar 

  19. S. Nowick, K. Yun, and D. Dill, “Practical Asynchronous Controller Design,” Proc. of the Intl. Conf. on Computer Design, Oct. 1992, pp. 341–345.

  20. E.M. Sentovich, K.J. Singh, C. Moon, H. Savoj, R.K. Brayton, and A. Sangiovanni-Vincentelli, “Sequential Circuit Design Using Synthesis and Optimization,” Proc. of the Intl. Conf. On Computer Design, Oct. 1992, pp. 328–333.

  21. R.K. Brayton, G.D. Hachtel, C.T. McMullen, and A.L. Sangiovanni-Vincentelli, Logic Minimization Algorithms for VLSI Synthesis, Kluwer Academic Publishers, Boston, MA, 1984.

    Google Scholar 

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Banerjee, S., Roy, R.K. & Chakradhar, S.T. Initialization issues in asynchronous circuit synthesis. J Electron Test 9, 237–250 (1996). https://doi.org/10.1007/BF00134689

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  • DOI: https://doi.org/10.1007/BF00134689

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