Abstract
In this article we discuss a test generation, design-for-testability and built-in self-test methodology for two-dimensional iterative logic arrays (ILAs) that perform arithmetic functions. Our approach is unique because a single graph labeling procedure is used to generate test vectors, implement design-for-testability as well as design the circuitry for built-in self-test. The graph labeling is based on mathematical properties of full-addition such as symmetry and self-duality. Circuit modifications are introduced by a systematic procedure based on the graph labeling, that enable them to be tested with a fixed number of tests irrespective of their size. The approach is novel as it also greatly simplifies the processes of on-chip test vector generation and response comparison that are necessary for built-in self-test. Each circuit module is tested in a pseudo-exhaustive manner with deterministic as opposed to random test sequences. This results in a comprehensive test of the circuit for which built-in self-test is designed.
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This research was supported by the General Electric Company and by the Semiconductor Research Corporation under contracts SRC RSCH 88-DP-108 at the University of Illinois and SRC RSCH 89-DP-142 at the University of Texas at Austin.
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Chatterjee, A., Abraham, J.A. Test generation, design-for-testability and built-in self-test for arithmetic units based on graph labeling. J Electron Test 2, 351–372 (1991). https://doi.org/10.1007/BF00135230
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DOI: https://doi.org/10.1007/BF00135230