Abstract
Advances in VLSI technology require changes in circuit test application methods or apparatus. The use of on-chip testing, called Built-in Testing or Built-in Self-Testing (BIST), has become popular. BIST techniques compact the output response of the circuit under test (CUT). Here we discuss a time compaction method called Hamming count (H-count). H-count encompasses all syndrome detectable faults. Simulation results and theoretical analysis illustrate the overall fault-detection potential of Hamming count. The proposed method presents simple and effective compaction technique.
Since BIST methods use productive chip area, a prime concern is providing the test results using the minimal amount of space. Hardware overhead reduction through counter elimination is considered for the Hamming Count compaction test. Intelligent counter selection is necessary to minimize the impact this hardware reduction has on fault detection. A method for selecting the most advantageous syndrome and input variable counter combination to utilize as a reduced H-count test is introduced. Analysis shows that the proposed method produces an optimal pairing. The paired counters have an aliasing probability which is half an order less than that of an unmodified syndrome test with exhaustive inputs. Adaptations in the counter selection method are made using a greedy strategy for choosing multiple counters to combine with the syndrome counter.
Similar content being viewed by others
References
S.B. Akers, “A parity bit signature for exhaustive testing,” Proc. Intern. Test Conf., pp. 48–83, 1986.
P.H. Bardell, W.H. McAnney and J. Savir, Built-in Test for VLSI—Pseudorandom Techniques, John Wiley & Sons, New York, 1987.
R. Bennetts and S.L. Hurst, “Rademacher-Walsh spectral transforms: A new tool for problems in digital-network faults diagnosis?,” Computers and Digital Techniques, vol. 1, pp. 38–44, May 1978.
B.B. Bhattacharya and S.C. Seth, “Design of parity testable combinational circuits,” IEEE Transactions on Computers, vol. 38, pp. 1580–1584, November 1989.
W.C. Carter, “Signature testing with guaranteed bounds for fault coverage,” Proc. Intern. Test Conf., IEEE, pp. 75–82, November 1982.
A. Gleason, “Hamming count—a proposed method for built in self-testing of VLSI,” Ph.D. Dissertation, Dept. of Comp. Sci., New Mexico Inst. of Mining and Tech., Socorro, NM, May 1991.
A. Gleason and W.B. Jone, “Hamming count—a compaction testing technique,” Proc. Intern. Conf. Comput. Design, pp. 344–347, October 1989.
I.S. Gupta, “Index vector testing of combinational circuits,” Proc. Intern. Test Conf., pp. 1108–1112, 1987.
T.-C. Hsiao and S.C. Seth, “Analysis of the use of Rademacher-Walsh spectrum in compact testing,” IEEE Transactions on Computers, vol. C-33, pp. 934–937, October 1984.
S.L. Hurst, D.M. Miller, and J.C. Muzio, Spectral Techniques in Digital Logic, Academic Press, New York, 1985.
W.B. Jone, “DSC—a space compression method,” Proc. 1990 Intern. Symp. on Circuits and Systems, pp. 2756–2759, 1990.
Y.K. Li and J.P. Robinson, “Space compression methods with output data modification,” IEEE Transactions on Computer-Aided Design, vol. CAD-6, pp. 290–294, March 1987.
E.J. McCluskey, “Built-in self-test techniques,” IEEE Design & Test of Computers, vol. 2, pp. 21–28, April 1985.
J.P. Robinson and N.R. Saxena, “A unified view of test compression methods,” IEEE Transactions on Computers, vol. C-36, pp. 94–99, January 1987.
J.P. Robinson and N.R. Saxena, “Simultaneous signature and syndrome compression,” IEEE Transactions on Computer-Aided Design, vol. 7, pp. 584–589, May 1988.
J. Savir, “Syndrome-testable design of combinational circuits,” IEEE Transactions on Computers, C-29(6):442–451, June 1980. See also, IEEE Transactions on Computers, vol. C-29, pp. 1012–1013, November 1980.
N.R. Saxena and J.P. Robinson, “Accumulator compression testing,” IEEE Transactions on Computers, vol. C-35, pp. 317–321, April 1986.
M. Serra and J.C. Muzio, “Space compaction for multiple-output circuits,” IEEE Transactions on Computer-Aided Design, vol. CAD-7, pp. 1105–1113, October 1988.
A.K. Susskind, “Testing by verifying Walsh coefficients,” IEEE Transactions on Computers, vol. C-32, pp. 198–201, February 1983.
T.W. Williams, “VLSI testing,” Computer, vol. 17, pp. 126–136, October 1984.
Author information
Authors and Affiliations
Additional information
This work was funded in part by Sandia National Laboratory under contract SANDIA-27-6108.
Rights and permissions
About this article
Cite this article
Jone, WB., Gleason, A. Analysis of Hamming count compaction scheme. J Electron Test 2, 373–384 (1991). https://doi.org/10.1007/BF00135231
Received:
Revised:
Issue Date:
DOI: https://doi.org/10.1007/BF00135231