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Diagnostic simulation of stuck-at faults in combinational circuits

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Abstract

Two faults are said to be equivalent, with respect to a test set τ, iff they cannot be distinguished by any test in τ. The sizes of the corresponding equivalence classes of faults are used as a basis for comparing the diagnostic capability of two given test sets. A novel algorithm, called “multiway list splitting,” for computing the Equivalence Classes of stuck-at faults, in combinational (full scan) circuits, with respect to a given test set is presented. Experimental results presented show the algorithm to be more efficient than previously known algorithms based on decision diagrams and diagnosibility matrix.

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Authors and Affiliations

  1. State University of New York, 14260, Buffalo, NY, USA

    Sreejit Chakravarty & Yiming Gong

  2. Center for Reliable and High-Performance Computing, University of Illinios, 61801, Urbana, IL, USA

    Srikanth Venkataraman

Authors
  1. Sreejit Chakravarty
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  2. Yiming Gong
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  3. Srikanth Venkataraman
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Additional information

Portions of this work were presented in [1].

Research Supported by NFS Grant No. MIP9102509.

Research Supported by SRC Grant 93-DP-109.

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Chakravarty, S., Gong, Y. & Venkataraman, S. Diagnostic simulation of stuck-at faults in combinational circuits. J Electron Test 8, 87–97 (1996). https://doi.org/10.1007/BF00136078

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  • DOI: https://doi.org/10.1007/BF00136078

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