Skip to main content

Advertisement

Springer Nature Link
Log in

The probability of error detection in sequential circuits using random test vectors

  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

    We’re sorry, something doesn't seem to be working properly.

    Please try refreshing the page. If that doesn't work, please contact support so we can address the problem.

Abstract

In this article a method is presented for evaluating the probability of detecting (PD) a single stuck-fault in a sequential circuit as a function of the number of random input test vectors. A discrete parameter Markov-model is used in the analysis to obtain closed-form expressions for PD. The circuit is partitioned into three parts, the input and output combinational logic and the memory. The analysis is based upon the stationary-state transition matrix associated with a circuit, and the probability that a fault in one of the partitions produces an error at the output of that partition when a random input vector is applied. Results are presented to show how this problem can be reduced to that of testing an equivalent combinational circuit.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Subscribe and save

Springer+ Basic
$34.99 /Month
  • Get 10 units per month
  • Download Article/Chapter or eBook
  • 1 Unit = 1 Article or 1 Chapter
  • Cancel anytime
Subscribe now

Buy Now

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. M. Abramovici, M.A. Breuer, and A.D. Friedman, Digital Systems Testing and Testable Designs, Computer Science Press, New York, 1990.

    Google Scholar 

  2. P. Agrawal and V.D. Agrawal, “Probabilistic analysis of random test generation method for irredundant combinational logic networks,” IEEE Trans. Comput. C-24 (7): 691–695, 1975.

    Google Scholar 

  3. V.D. Agrawal and S.C. Seth, Test Generation for VLSI Chips, IEEE Computer Society Press, Los Alamitos, CA, 1988.

    Google Scholar 

  4. G. Blanchet and R. David, “About random fault detection in combinational network,” IEEE Trans. Comput. C-25 (6): 659–664, 1976.

    Google Scholar 

  5. M.A. Breuer and A.A. Ismaeel, “Roving emulation as a fault detection mechanism,” IEEE Trans. Comput. C-35 (11): 933–939, 1986.

    Google Scholar 

  6. S.R. Das and W.B. Jone, “Modified transition matrix and fault testing in sequential logic circuits under random stimuli with a specified measure of confidence,” Cybernetics and Systems 17 (1): 1–12, 1986.

    Google Scholar 

  7. S.R. Das, W.B. Jone, and K.L. Wong, “Probabilistic modeling and fault analysis in sequential logic using computer simulation.” In Intern. Conf. Comput. Aided Design, Modeling and Simulation, pp. 87–93, June 1986.

  8. R. David and P. Thevenod-Fosse, “A method to analyze random testing of sequential circuits,” Digital Processes 4: 313–332, 1978.

    Google Scholar 

  9. W. Feller, An Introduction to Probability Theory and Its Applications, Vol. 1, John Wiley & Sons, New York, 1968.

    Google Scholar 

  10. A.A. Ismaeel, Roving emulation: theory and analysis, Ph.D. thesis, University of Southern California, August 1983.

  11. S.K. Jain and V.D. Agrawal, “Statistical fault analysis,” IEEE Design and Test Comput. 2: 39–44, June 1985.

    Google Scholar 

  12. J. Losq, “Efficiency of compact testing for sequential circuit.” In Proc. 6th Intern. Symp. Fault-Tolerant Comput., pp. 168–174, June 1976.

  13. K.P. Parker and E.J. McCluskey, “Analysis of logic circuits with faults using input signal probabilities,” IEEE Trans. Comput. C-24 (5): 573–578, 1975.

    Google Scholar 

  14. J.C. Rault, “A graph theoretical and probabilistic approach to the fault detection of digital circuits.” In Proc. 1st Intern. Symp. Fault-Tolerant Comput. pp. 26–29, March 1971.

  15. J. Savir, G. Ditlow, and P. Bardell, “Random pattern testability,” IEEE Trans. Comput. C-33 (1): 79–90, 1984.

    Google Scholar 

  16. S.C. Seth, L. Pan, and V.D. Agrawal, “Predict-probabilistic estimation of digital circuit testability.” In 15th Intern. Symp. Fault-Tolerant Comput., pp. 220–225, June 1985.

  17. J.J. Shedletsky and E.J. McCluskey, “The error latency of a fault in a sequential digital circuit,” IEEE Trans. Comput. C-25 (6): 655–659, 1976.

    Google Scholar 

  18. P. Thevenod-Fosse and R. David, “Random testing of integrated circuits,” IEEE Trans. Instrument. Measur. 30: 20–25, March 1981.

    Google Scholar 

  19. T.K. Truong, L.J. Deutch, I.S. Reed, J.S. Hsu, K. Wang, and C.S. Yeh, “The VLSI design of a Reed-Solomon encoder using Berlekamp's bit serial algorithm,” IEEE Trans. Comput. C-33 (10): 906–911, 1984.

    Google Scholar 

  20. H.J. Wunderlich and S. Hellebrand, “The pseudo-exhaustive test of sequential circuits,” Proc. Intern. Test Conf., pp. 19–27, 1989.

Download references

Author information

Authors and Affiliations

  1. Kuwait University, Kuwait

    Asad A. Ismaeel

  2. Electrical Engineering-Systems Department, University of Southern California, 90089-0781, Los Angeles, CA, USA

    Melvin A. Breuer

Authors
  1. Asad A. Ismaeel
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Melvin A. Breuer
    View author publications

    You can also search for this author in PubMed Google Scholar

Rights and permissions

Reprints and permissions

About this article

Cite this article

Ismaeel, A.A., Breuer, M.A. The probability of error detection in sequential circuits using random test vectors. J Electron Test 1, 245–256 (1991). https://doi.org/10.1007/BF00136314

Download citation

  • Received:

  • Revised:

  • Issue Date:

  • DOI: https://doi.org/10.1007/BF00136314

Key words

Search

Navigation