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A test methodology for finite state machines using partial scan design

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Abstract

This paper presents an efficient automatic test pattern generation technique for loop-free circuits. A partial scan technique is used to convert a sequential circuit (finite state machine) with arbitrary feedback paths into a pipelined circuit for testing. Test generation for these modified circuits can be performed with a modified combinational automatic test pattern generator (ATPG), which is much faster than a sequential ATPG. A combinational model is obtained by replacing all flipflops by buffers. It is shown that a test vector for a fault in this model obtained by a combinational test generator can be expanded into a sequence of identical vectors to detect the same fault in the original sequential circuit. This technique may abort a few faults which can then be resolved with a sequential ATPG. Experiments on the ISCAS89 circuits show that only 30% to 70% of flipflops require scanning in larger circuits and 96% to 100% fault coverage for almost all the circuits without resorting to a sequential ATPG.

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, Cheon-Cheon-Dong 300, Su Win City, Kyungki-do, Korea

    Hyoung B. Min

  2. Department of Electrical and Computer Engineering, Computer Enginering Research Center, University of Texas, 78758, Austin, TX, USA

    William A. Rogers

Authors
  1. Hyoung B. Min
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  2. William A. Rogers
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Additional information

This research was sponsored by the Semiconductor Research Corporation, Contract 90-DP-142.

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Min, H.B., Rogers, W.A. A test methodology for finite state machines using partial scan design. J Electron Test 3, 127–137 (1992). https://doi.org/10.1007/BF00137250

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  • DOI: https://doi.org/10.1007/BF00137250

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