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Counter-based compaction: An analysis for BIST

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Abstract

According to some recently published results, counter-based compaction outperforms compaction by linear feedback shift registers. These results, however, are based on oversimplified assumptions. In this paper, we discuss an error model to describe the behavior of a faulty circuit under test. We study the three most popular counter-based compaction schemes, (i.e., one's counting, transition counting and edge counting). Using Markov processes we derive equations for iterative computations of exact aliasing probability for any test session length and determine the asymptotic probability of aliasing. For one's counting, we also present a closed form expression that, for any test session length, gives the exact aliasing probability. Finally, we present some examples to compare the aliasing in the counter-based compaction and compaction by a linear feedback shift register. These examples indicate that aliasing by LFSRs is more “predictable” than aliasing by counters.

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References

  1. J. Savir, “Syndrome-testable design of combinational circuits,”IEEE Trans. Comput., vol. C-29, pp. 442–451, June 1980.

    Google Scholar 

  2. P.M. Bardell, W.H. McAnney, and J. Savir,Built-In Test for VLSI: Pseudorandom Techniques. New York: John Wiley & Sons, 1987.

    Google Scholar 

  3. M. Abramovici, M.A. Breuer, and A.D. Friedman,Digital Systems Testing and Testable Design. New York: Computer Science Press, 1990.

    Google Scholar 

  4. J. Savir and W.H. McAnney, “On the masking probability with one's count and transition count,” inProc. Int'l Conf. on Computer-Aided Design, pp. 111–113, November 1985.

  5. R.C. Aitken and V.K. Agarwal, “Aliasing probability of nonexhaustive randomized syndrome test,” inProc. Int'l. Conf. on Computer-Aided Design, pp. 232–235, November 1988.

  6. H. Fujiwara and K. Kinoshita, “Testing logic circuits with compressed data,” inProc. Fault-Tolerant Computing Symp. pp. 108–113, June 1978.

  7. R. A. Frohwerk, “Signature analysis: A new digital field service method,”Hewlett-Packard Journal, vol. 28, pp. 2–8, May 1977.

    Google Scholar 

  8. K. Iwasaki, “Analysis and proposal of signature circuits for LSI testing,”IEEE Trans. CAD, vol. 7, pp. 84–90, January 1988.

    Google Scholar 

  9. M. Damiani, P. Olivo, M. Favalli, and B. Riccó, “An analytical model for the aliasing probability signature analysis testing,”IEEE Trans. CAD, vol. 8, pp. 842–859, August 1989.

    Google Scholar 

  10. A. Hlawiczka, “Hybrid design of parallel signature analyzers,” inProc. European Test Conf. pp. 354–360, April 1989.

  11. T.W. Williams, W. Daehn, M. Gruetzner, and C.W. Starke, “Bounds on aliasing for linear feedback shift registers,”IEEE Trans. CAD, vol. 7, pp. 75–83, January 1988.

    Google Scholar 

  12. A. Ivanov and V.K. Agarwal, “An analysis of the probabilistic behavior of linear feedback signature registers,”IEEE Trans. CAD, vol. 8, pp. 1074–1088, October 1989.

    Google Scholar 

  13. K. Iwasaki and F. Arakawa, “An analysis of the aliasing probability of multiple-input signature registers in the case of a 2m-ary symmetric channel,”IEEE Trans. CAD, vol. 9, pp. 427–438, April 1990.

    Google Scholar 

  14. D.K. Pradhan, S.K. Gupta, and M.G. Karpovsky, “Aliasing probability for multiple input signature analyzer,”IEEE Trans. Comput., vol. 39, pp. 586–592, April 1990.

    Google Scholar 

  15. W. Daehn, T.W. Williams, and K.D. Wagner, “Aliasing errors in linear automata used as multiple-input signature analyzers,”IBM Journal of Research and Development, vol. 34, pp. 363–380, March/May 1990.

    Google Scholar 

  16. J.P. Hayes, “Check sum test methods,” inProc. Fault-Tolerant Computing Symp., pp. 289–296, June 1976.

  17. J.P. Robinson and N.R. Saxena, “Simultaneous signature and syndrome compression,”IEEE Trans. CAD, vol. 7, pp. 584–589, May 1988.

    Google Scholar 

  18. J.C. Muzio, F. Ruskey, R.C. Aitken, and M. Serra, “Aliasing probabilities for some data compression techniques,” inDevelopments in IC Testing (D.M. Miller, ed.), London: Academic Press, 1987.

    Google Scholar 

  19. A. Ivanov and Y. Zorian, “Computing the error escape probability in count-based compaction schemes,” inProc. Int'l. Conf. on Computer-Aided Design, pp. 368–371, November 1990.

  20. Y. Zorian and V.K. Agarwal, “A general scheme to optimize error masking in built-in self-testing,” inProc. Fault-Tolerant Computing Symp., pp. 410–415, July 1986.

  21. R.C. Aitken, D. Xavier, A. Ivanov, and V.K. Agarwal, “The role of an asymmetric error model in predicting aliasing of built-in self-test for VLSI,” inProc. Canadian Conf. on Electrical and Computer Eng., pp. 356–361, September 1989.

  22. D. Xavier, R.C. Aitken, A. Ivanov, and V.K. Agarwal, “Experiments on aliasing in signature analysis,” inProc. Int'l. Test Conf. pp. 344–354, August 1989.

  23. T.W. Williams, W. Daehn, M. Gruetzner, and C.W. Starke, “Comparison of aliasing errors for primitive and nonprimitive polynomials,” inProc. Int'l. Test Conf., pp. 282–288, September 1986.

  24. R. David, “Comments on “Signature analysis for multiple output circuits”,”IEEE Trans. Comput., vol. 39, pp. 287–288, February 1990., pp. 282–288, September 1986.

    Google Scholar 

  25. S. Pilarski, T. Kameda, and A. Ivanov, “Sequential faults and aliasing,” Tech. Rep. CSS/LCCR TR 90-20, Simon Fraser University, November 1990.

  26. R. David, “Feedback shift register testing,” inProc. Fault-Tolerant Computing Symp., pp. 103–107, June 1978.

  27. M. Damiani, P. Olivo, and B. Riccó, “Analysis and design of linear finite state machines for signature analysis testing,”IEEE Trans. Comput., vol. 40, pp. 1034–1045, September 1991.

    Google Scholar 

  28. A. Ivanov and S. Pilarski, “Performance of signature analysis: a survey of bounds, exact and heuristic algorithms.”Integration, The VLSI Journal, to appear.

  29. T. Kameda, S. Pilarski, and A. Ivanov, “Notes on multiple input signature analysis,” Tech. Rep. CSS/LCCR TR 90-16, Simon Fraser University, July 1990.

  30. W. Feller,An Introduction to Probability Theory and Its Applications, vol. 1. New York: John Wiley & Sons, 1950.

    Google Scholar 

  31. F. Brglez and H. Fujiwara, “A neutral netlist of 10 combinational benchmark circuits and a target translator in FORTRAN,” inProc. IEEE Int. Symp. Circuits and Systems, pp. 663–698, June 1985.

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  1. School of Computing Science, Simon Fraser University, V5A 1S6, Burnaby, B.C., Canada

    Slawomir Pilarski & Kevin James Wiebe

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  1. Slawomir Pilarski
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  2. Kevin James Wiebe
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Pilarski, S., Wiebe, K.J. Counter-based compaction: An analysis for BIST. J Electron Test 3, 33–43 (1992). https://doi.org/10.1007/BF00159829

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  • DOI: https://doi.org/10.1007/BF00159829

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