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Counter-based compaction: An analysis for BIST

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Abstract

According to some recently published results, counter-based compaction outperforms compaction by linear feedback shift registers. These results, however, are based on oversimplified assumptions. In this paper, we discuss an error model to describe the behavior of a faulty circuit under test. We study the three most popular counter-based compaction schemes, (i.e., one's counting, transition counting and edge counting). Using Markov processes we derive equations for iterative computations of exact aliasing probability for any test session length and determine the asymptotic probability of aliasing. For one's counting, we also present a closed form expression that, for any test session length, gives the exact aliasing probability. Finally, we present some examples to compare the aliasing in the counter-based compaction and compaction by a linear feedback shift register. These examples indicate that aliasing by LFSRs is more “predictable” than aliasing by counters.

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  1. School of Computing Science, Simon Fraser University, V5A 1S6, Burnaby, B.C., Canada

    Slawomir Pilarski & Kevin James Wiebe

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  1. Slawomir Pilarski
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  2. Kevin James Wiebe
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Pilarski, S., Wiebe, K.J. Counter-based compaction: An analysis for BIST. J Electron Test 3, 33–43 (1992). https://doi.org/10.1007/BF00159829

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  • DOI: https://doi.org/10.1007/BF00159829

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