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MT-SIM a mixed-level transition fault simulator based on parallel patterns

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Abstract

This paper describes a mixed level, (i.e., switch-level and gate-level) transition fault simulator based on parallel patterns: MT-SIM. The switch-level allows the simulator to treat faults at the transistor level, while the gate-level conserves the simulation speed and the parallel pattern strategy further enhances the simulation speed for more than one order of magnitude. The simulator is built based on a set of operators which translate the switch-level signal propagation into Boolean operations and transform the gate-level logic elements into symbolic logic representations. The experimental results of the simulator show that it can exhibit a linear performance for the logic-level simulation if a longer word length is adopted.

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Authors and Affiliations

  1. Department of Electronics, National Chiao Tung University, Hsin-Chu, Taiwan, R.O.C.

    Chung Len Lee, Ching Ping Wu, Wen Zen Shen, Tyh Song Hwang & Shueng Dar Hwang

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  1. Chung Len Lee
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  2. Ching Ping Wu
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  3. Wen Zen Shen
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  4. Tyh Song Hwang
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  5. Shueng Dar Hwang
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Lee, C.L., Wu, C.P., Shen, W.Z. et al. MT-SIM a mixed-level transition fault simulator based on parallel patterns. J Electron Test 3, 67–78 (1992). https://doi.org/10.1007/BF00159832

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  • DOI: https://doi.org/10.1007/BF00159832

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