Abstract
This paper describes a mixed level, (i.e., switch-level and gate-level) transition fault simulator based on parallel patterns: MT-SIM. The switch-level allows the simulator to treat faults at the transistor level, while the gate-level conserves the simulation speed and the parallel pattern strategy further enhances the simulation speed for more than one order of magnitude. The simulator is built based on a set of operators which translate the switch-level signal propagation into Boolean operations and transform the gate-level logic elements into symbolic logic representations. The experimental results of the simulator show that it can exhibit a linear performance for the logic-level simulation if a longer word length is adopted.
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References
R.E. Bryant, “An algorithm for MOS logic simulation,”Lambda, 4th qtr., pp. 46–53, 1980.
Z. Barzilai, D.K. Beece, L.M. Huisman, V.S. Iyengar, and G.M. Siberman, “SLS-A fast switch level simulator for verification and fault coverage analysis,”Proc. Design Automation Conf., pp. 164–170, 1986.
C.J. Terman, “RSIM-A logic-level timing simulator,”Proc. Int'l. Conf. Computers and Design, pp. 437–440, 1983.
A.K. Bose, P. Kozak, C-Y Lo, H.N. Nham, E. Pascas-Skewes, and K. Wu, “A fault simulator for MOS LSI circuits,”Proc. of 19th Design Automation Conf., pp. 400–409, 1982.
R.E. Bryant, and M.D. Shuster, “Performance evaluation of FMOSSIM, a concurrent switch-level fault simulator,”Proc. Design Automation Conf., pp. 715–719, 1985.
D. Saab, and T. Hajj, “Parallel and concurrent fault simulation of MOS circuits,”Proc. Int'l. Conf. Computers and Design, pp. 752–756, 1984.
J.D. Lesser and J.J. Shedletsky, “An experimental delay test generator for LSI logic,”IEEE Trans. on Computers, vol. c-29, pp. 235–248, 1980.
T. Hayashi, K. Hatayama, K. Sato and T. Natabe, “A delay test generator for logic LSI,”Proc. 14th Int'l. Conf. Fault-Tolerant Computing, pp. 146–149, 1984.
Y.K. Malaiya and R. Narayanaswamy, “Modeling and testing for timing faults in synchronous sequential circuits,”IEEE Design & Test, pp. 62–74, November 1984.
G.L. Smitch, “Model for delay faults based on paths,”Proc. Int'l. Test Conf., pp. 342–349, 1985.
J.A. Waicukauski, E. Lindbloom, B. Rosen, and V. Iyengar, “Transition fault simulation by parallel pattern single fault propagation,”Proc. Int'l. Test Conf., pp. 542–549, 1986.
Y. Levendel and P.R. Menon, “Transition faults in combinational circuits: input transition test generation and feult simulation,”Proc. 16th Int'l. Conf. Fault-Tolerant Computing, pp. 278–283, 1986.
J.L. Carter, V.S. Iyengar, and B.K. Rosen, “Efficient test coverage determination for delay faults,”Proc. Int'l. Test Conf., pp. 418–427, 1987.
E.S. Park and M.R. Mercer, “Robust and nonrobust tests for path delay faults in a combinational circuit,”Proc. Int'l. Test Conf., pp. 1027–1034, 1987.
C.J. Lin and S.M. Reddy, “On delay fault testing in logic circuits,”IEEE Transition Computer-Aided Design, vol. CAD-6, pp. 694–703, 1987.
A.K. Pramanick and S.M. Reddy, “On detection of delay faults,”Proc. Int'l. Test Conf., pp. 845–856, 1988.
V.S. Iyengar, B.K. Rosen and J.A. Waicukauski, “On computing the sizes of detected delay faults,”IEEE Trans. on ComputerAided Design, vol. CAD-9, pp. 299–312, 1990.
T.S. Hwang, C.L. Lee, W.Z. Shen, C.P. Wu, “A parallel pattern mixed-level fault simulator,”27th Design Automation Conf., June 1990, pp. 716–719.
J.E. Chen, C.L. Lee and W.Z. Shen, “My_Box representation for faulty CMOS circuits,”Proc. of IEE, Part G, vol. 137, no. 3, June 1990, pp. 225–232.
F. Brglez, and H. Fujiwa, “A Neutral Netlist of 10 combination benchmark circuits and a target translator in FORTRAN,”Proc. ISCAS, 1985.
D. Harel, “Is there hope for linear time fault simulation?,”Fault Tolerant Computing Symposium, FTCS-17, pp. 28–33, 1987.
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Lee, C.L., Wu, C.P., Shen, W.Z. et al. MT-SIM a mixed-level transition fault simulator based on parallel patterns. J Electron Test 3, 67–78 (1992). https://doi.org/10.1007/BF00159832
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DOI: https://doi.org/10.1007/BF00159832