Abstract
Two algorithms for fault simulation of combinational networks on massively parallel SIMD machines are presented. One algorithm uses a variant of the PPSFP [1] approach, while the other uses a mixture of parallel fault simulation [2] and PPSFP [1]. The algorithms have been implemented on the [Thinking Machines Corporation's] Connection Machine [3]. The second algorithm compares very favorably with published results for well known serial algorithms on the ISCAS benchmark circuits [4]. The results indicate that parallel processing could be a valuable tool for accelerating VLSI CAD applications.
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Narayanan, V., Pitchumani, V. Fault simulation on massively parallel SIMD machines algorithms, implementations and results. J Electron Test 3, 79–92 (1992). https://doi.org/10.1007/BF00159833
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DOI: https://doi.org/10.1007/BF00159833