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The derivation of systolic implementations of programs

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Summary

We present a mathematically rigorous and, at the same time, convenient method for systolic design and derive systolic designs for three matrix computation problems. Each design is synthesized from a simple program and a proposed layout of processors. The synthesis derives a systolic parallel execution, channel connections for the proposed processor layout, and an arrangement of data streams such that the systolic execution can begin. Our choices of designs are governed by formal theorems. The synthesis method is implementable and is particularly effective if implemented with graphics capability. Our implementation on the Symbolics 3600 displays the resulting designs and simulated executions graphically on the screen. The method's centerpiece, a transformation of sequential program computations into systolic parallel ones, has been mechanically proved correct.

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References

  1. Boyer, R.S., Moore, J.S.: A Computational Logic. ACM Monograph Series. New York: Academic Press 1979

    Google Scholar 

  2. Cappello, P.R., Steiglitz, K.: Unifying VLSI Array Design with Linear Transformations of Space-time. In: Advances in Computing Research, F.P. Preparata, (ed.) VLSI Theory, Vol. 2, pp. 23–65. Greenwich, CT: JAI Press Inc. 1984

    Google Scholar 

  3. Chandy, M.: Concurrent Programming for the Masses. Proc. 4th Ann. ACM Symp. on Principles of Distributed Computing, pp. 1–12 (1985)

  4. Chandy, K.M., Misra, J.: Systolic Algorithms as Programs. Distrib. Comput. 1, 3, 177–183 (1986)

    Google Scholar 

  5. Chen, M.C.: Synthesizing Systolic Designs. YALEU/DCS/RR-374, Department of Computer Science, Yale University, March 1985

  6. Chen, M.C.: A Parallel Language and Its Compilation to Multiprocessor Machines or VLSI. Proc. 13th Ann. ACM Symp. on Principles of Programming Languages, pp. 131–139 (1986)

  7. Delosme, J.-M., Ipsen, I.C.F.: Design Methodology for Systolic Arrays. Proc. SPIE Symposium, Vol. 696, Advanced Algorithms and Architectures for Signal Processing, pp. 245–259 (1986)

  8. Fortes, J.A.B., Moldovan, D.I.: Parallelism Detection and Transformation Techniques for VLSI Algorithms. J. Parallel Distrib. Comput. 2, 277–301 (1985)

    Google Scholar 

  9. Huang, C.-H., Lengauer, C.: An Incremental, Mechanical Development of Systolic Solutions to the Algebraic Path Problem. TR-86-28, Department of Computer Sciences, The University of Texas at Austin, December 1986

    Google Scholar 

  10. Huang, C.-H., Lengauer, C.: An Implemented Method for Incremental Systolic Design. In: Parallel Architectures and Languages Europe (PARLE). J.W. de Bakker, A.J. Nijman, P.C. Treleaven, (eds.) Parallel Architectures, Vol. 1, pp. 160–177, Lecture Notes in Computer Science 258. Berlin, Heidelberg, New York, Tokyo: Springer 1987

    Google Scholar 

  11. Knuth, D.E.: The Art of Computer Programming, Vol. 3: Sorting and Searching Sect. 5.3.4. Reading, MA: Addison-Wesley 1973

    Google Scholar 

  12. Kung, H.T., Leiserson, C.E.: Algorithms for VLSI Processor Arrays. In: Introduction to VLSI Systems, Sect. 8.3., C. Mead, L. Conway (eds.). Reading, MA: Addison-Wesley 1980

    Google Scholar 

  13. Lam, M.S., Mostow, J.: A Transformational Model of VLSI Systolic Design. Computer 18, 42–52 (1985)

    Google Scholar 

  14. Leiserson, C.E.: Systolic and Semisystolic Design (Extended Abstract). Proc. IEEE Int. Conf. on Computer Design/VLSI in Computers, pp. 627–632 (ICCD '83), 1983

  15. Leiserson, C.E., Saxe, J.B.: Optimizing Synchronous Systems. J. VLSI Comput. Syst. 1, 41–67 (1983)

    Google Scholar 

  16. Lengauer, C.: A Methodology for Programming with Concurrency: The Formalism. Sci. Comput. Programming 2, 19–52 (1982)

    Google Scholar 

  17. Lengauer, C., Huang, C.-H.: A Mechanically Certified Theorem about Optimal Concurrency of Sorting Networks. Proc. 13th Ann. ACM Symp. on Principles of Programming Languages, pp. 307–317 (1986)

  18. Li, G.-H., Wah, B.W.: The Design of Optimal Systolic Arrays. IEEE Trans. Comput. 34, 66–77 (1985)

    Google Scholar 

  19. Miranker, W.L., Winkler, A.: Spacetime Representations of Computational Structures. Computing 32, 93–114 (1984)

    Google Scholar 

  20. Moldovan, D.I.: On the Design of Algorithms for VLSI Systolic Arrays. Proc. IEEE 71, 113–120 (1983)

    Google Scholar 

  21. Moldovan, D.I., Fortes, J.A.B.: Partitioning and Mapping Algorithms into Fixed Size Systolic Arrays. IEEE Trans. Comput. 35, 1–12 (1986)

    Google Scholar 

  22. Quinton, P.: The Systematic Design of Systolic Arrays. TR84-11, Microelectronics Center of North Carolina, May 1984

  23. Rao, S.K.: Regular Iterative Algorithms and their Implementations on Processor Arrays. Ph.D. Thesis, Department of Electrical Engineering, Stanford University, October 1985

  24. Rote, G.: A Systolic Array Algorithm for the Algebraic Path Problem (Shortest Paths; Matrix Inversion). Computing 34, 191–219 (1985)

    Google Scholar 

  25. van de Snepscheut, J.L.A.: A Derivation of a Distributed Implementation of Warshall's Algorithm. Sci. Comput. Programming 7, 55–60 (1986)

    Google Scholar 

  26. Weiser, U., Davis, A.: A Wavefront Notation Tool for VLSI Array Design. In: VLSI Systems and Computations, H.T. Kung, B. Sproull, G. Steele (eds.) Rockville, MA: Computer Science, pp. 226–234. Press 1981

    Google Scholar 

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Huang, CH., Lengauer, C. The derivation of systolic implementations of programs. Acta Informatica 24, 595–632 (1987). https://doi.org/10.1007/BF00282618

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