Abstract
Speed-independent circuit design is of increasing interest because of global timing problems in VLSI. Unfortunately, speed-independent design is very subtle. We propose the use of statemachine verification tools to ameliorate this problem. This article illustrates issues in the modeling, specification, and verification of speed-independent circuits through consideration of self-timed queues. User-level specifications are given as Petri nets, which are translated into trace structures for automatic processing. Three different implementations of queues are considered: a chain of queue cells, two parallel chains, and a “circular buffer” example using a separate RAM.
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Dill, D.L., Nowick, S.M. & Sproull, R.F. Specification and automatic verification of self-timed queues. Form Method Syst Des 1, 29–60 (1992). https://doi.org/10.1007/BF00464356
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DOI: https://doi.org/10.1007/BF00464356