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β-bit serial/parallel multipliers

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Abstract

A generalized β-bit least-significant-digit (LSD) first, serial/parallel multiplier architecture is presented with 1≤β≤n wheren is the operand size. The multiplier processes both the serial input operand and the double precision product β-bits per clock cycle in an LSD first, synchronous fashion. The complete two's complement double precision product requires 2n/β clock cycles. This generalized architecture creates a continuum of multipliers between traditional bit-serial/parallel multipliers (β=1) and fully-parallel multipliers (β=n). β-bit serial/parallel multipliers allow anoptimized integrated circuit arithmetic to be designed based on a particular application's area, power, throughput, latency, and numerical precision constraints.

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, University of California, San Diego, 92093, La Jolla, California

    Richard C. North & Walter H. Ku

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  1. Richard C. North
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  2. Walter H. Ku
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This project was pratically funded by the UCSD-NSF I/UCR Center on Ultra-High Speed Intergrated Circuits and Systems.

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North, R.C., Ku, W.H. β-bit serial/parallel multipliers. J VLSI Sign Process Syst Sign Image Video Technol 2, 219–233 (1991). https://doi.org/10.1007/BF00925467

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  • DOI: https://doi.org/10.1007/BF00925467

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