Abstract
This paper presents the Wafer Scale Integration research underway at our university. Specifically, we focus here on theApplications, Architectures, Design, and Test areas. Discussed are the philosophy of such an—admittedly aggressive—effort, the evolving infrastructure for the project, the application-driven architectures developed, and the design and test methodology. The first WSI design is a fully parallel FFT wafer, with application to a high-performance, high-speed CW jamming canceller. Other wafer level designs include an L-U decomposition array, using a newly-developed reciprocal cell, and a multipurpose PE array. The transition from basic tools, such as MAGIC, to commercial tools such as CADENCE, and the importance of a high level description language, VHDL, for modeling and simulation is emphasized. The discipline of reconfiguration, and the associated yield models, incorporating a harvesting factor, are also an integral part of the on-going project. Although, the first wafer will be reconfigured usingLaser linking and Cutting on the in-house laser table, alternative recon-figuration approaches for the other wafer designs are also being considered.
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This research was supported by DARPA grant #MDA 972-88-J-1006. A part of this research was also supported by the Florida High Technology and Industry Council.
An erratum to this article is available at http://dx.doi.org/10.1007/BF00936907.
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Jain, V.K., Landis, D.L., Keezer, D.C. et al. Wafer Scale Integration: A university perspective. J VLSI Sign Process Syst Sign Image Video Technol 2, 253–269 (1991). https://doi.org/10.1007/BF00925469
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DOI: https://doi.org/10.1007/BF00925469