Skip to main content
SpringerLink
Log in

A sorter-based architecture for a parallel implementation of communication intensive algorithms

  • Published:
Journal of VLSI signal processing systems for signal, image and video technology Aims and scope Submit manuscript

Abstract

This paper deals with the parallel execution of algorithms with global and/or irregular data dependencies on a regularly and locally connected processor array. The associated communication problems are solved by the use of a two-dimensional sorting algorithm. The proposed architecture, which is based on a two-dimensional sorting network, offers a high degree of flexibility and allows an efficient mapping of many irregularly structured algorithms. In this architecture a one-dimensional processor array performs all required control and arithmetic operations, whereas the sorter solves complex data transfer problems. The storage capability of the sorting network is also used as memory for data elements. The algorithms for sparse matrix computations, fast Fourier transformation and for the convex hull problem, which are mapped onto this architecture, as well as the simulation of a shared-memory computer show that the utilization of the most complex components, the processors, is O(1).

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. S.G. Akl, The Design and Analysis of Parallel Algorithms, Englewood Cliffs, NJ: Prentice-Hall, 1989.

    MATH  Google Scholar 

  2. K.E. Batcher, “Sorting Networks and Their Applications,”Proc. AFIPS Spring Joint Computer Conf. 32, 1968, pp. 307–314.

    Google Scholar 

  3. E. Bernard, “CMOS-Entwurf eines 2-dim. fehlertoleranten Sortiernetzwerkes für Datentransportaufgaben,” Diplomarbeit, TU München, 1990.

  4. G.E. Blelloch, “Scans as Primitive Parallel Operations,”IEEE Transactions on Computers, vol. 38, pp. 1526–1527, 1989.

    Article  Google Scholar 

  5. J. Götze and U. Schwiegelshohn, “Sparse-Matrix-Vector Multiplication on a Systolic Array,”Proc. of ICASSP, pp. 2061–2064, 1988.

  6. K. Hwang, P.-S. Tseng, and D. Kim, “An Orthogonal Multiprocessor for Parallel Scientific Computations,”IEEE Transactions on Computers, vol. 38, 1989, pp. 47–61.

    Article  MATH  Google Scholar 

  7. D.E. Knuth,The Art of Computer Programming, vol. 3: Sorting and Searching, Reading, MA: Addison Wesley, 1973.

    Google Scholar 

  8. J.G. Krammer, “Parallel Processing with a Sorting Network,”ISCAS, New Orleans, 1990, pp. 966–969.

    Google Scholar 

  9. J.G. Krammer and H. Arif, “A Fault-Tolerant Two-Dimensional Sorting Network,”Proc. of ASAP, 1990, pp. 317–328.

  10. M. Misra and V.K.P. Kumar, “Efficient VLSI Implementation of Iterative Solutions to Sparse Linear Systems,” Technical Report, IRIS no. 246, University of Southern California, 1988.

  11. D. Nassimi and S. Sahni, “An Optimal Routing Algorithm for Mesh-Connected Parallel Computers,”Journal of the ACM, vol. 30, 1980, pp. 6–29.

    Article  MathSciNet  Google Scholar 

  12. D. Nassimi and S. Sahni, “Bitonic Sort on a Mesh-Connected Parallel Computer,”IEEE Transactions on Computers, vol. 27, 1979, pp. 3–7.

    Google Scholar 

  13. M.C. Pease, “An adaptation of the fast Fourier transform for parallel processing,”Journal of the ACM, vol. 15, 1968, pp. 252–264.

    Article  MATH  Google Scholar 

  14. M.C. Pease, “The Indirect Binary n-Cube Microprocessor Array,”IEEE Transactions on Computers, vol. 26, 1977, pp. 458–473.

    Article  MATH  Google Scholar 

  15. F.P. Preparata and M.I. Shamos,Computational Geometry—An Introduction, New York: Springer-Verlag, 1985.

    Google Scholar 

  16. I.D. Scherson and S. Sen, “Parallel Sorting in Two-Dimensional VLSI Models of Computation,”IEEE Transactions on Computers, vol. 38, 1989, pp. 238–249.

    Article  MathSciNet  MATH  Google Scholar 

  17. U. Schwiegelshohn, “A Shortperiodic Two-Dimensional Systolic Sorting Algorithm,”Int. Conf. on Systolic Arrays, San Diego, Calif., 1988, pp. 257–264.

  18. H.S. Stone, “Parallel Processing with the Perfect Shuffle,”IEEE Transactions on Computers, vol. 20, 1971, pp. 153–161.

    Article  MATH  Google Scholar 

  19. G. Strang,Linear Algebra and Its Applications, New York: Academic Press, 1980.

    Google Scholar 

  20. C.D. Thompson and H.T. Kung, “Sorting on a Mesh-Connected Parallel Computer,”Comm. ACM, vol. 20, 1977, pp. 263–271.

    Article  MathSciNet  MATH  Google Scholar 

  21. C.D. Thompson, “The VLSI Complexity of Sorting,”IEEE Transactions on Computers, vol. 32, 1983, pp. 1171–1184.

    Article  MATH  Google Scholar 

  22. K.W. Przytula, J.G. Nash and S. Hansen, “Fast Fourier transforms algorithm for two-dimensional array of processors,”SPIE, vol. 826, 1987, pp. 186–198.

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Institute for Network Theory and Circuit Design, Technical University Munich, Arcisstr. 21, 8000, Munich 2, Germany

    Josef G. Krammer

Authors
  1. Josef G. Krammer
    View author publications

    You can also search for this author in PubMed Google Scholar

Rights and permissions

Reprints and permissions

About this article

Cite this article

Krammer, J.G. A sorter-based architecture for a parallel implementation of communication intensive algorithms. J VLSI Sign Process Syst Sign Image Video Technol 3, 93–103 (1991). https://doi.org/10.1007/BF00927837

Download citation

  • Received:

  • Revised:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/BF00927837

Keywords

Search

Navigation