Abstract
In the paper we show a single, efficient implementation of dynamic programming on alinear array using a new mapping methodology. In this method, we start with a known 2-D array onto which the dynamic programming algorithm has been mapped. By partitioning and stretching, this 2-D array is mapped onto a linear array. We derive a data movement scheme to simulate the data streams and the computations in the 2-D array. This scheme is implemented usingfast/slow data channels. Compared to known designs in the literature our design uses constant storage in each PE, constant number of I/O lines and continuous I/O sequence. Besides, the data and control flow in the array is unidirectional. This property makes the design suitable for implementation on the well-known fault-tolerant Wafer Scale Integration model.
Similar content being viewed by others
References
T.C. Hu,Combinatorial Algorithms. Reading, MA: Addison-Wesley, 1981.
D.E. Knuth,The Art of Computer Programming, vol. 3, Sorting and Searching, Reading, MA: Addison-Wesley, 1973.
P.J. Varman and I.V. Ramakrishnan, “Dynamic programming and transitive closure on linear pipelines,”International Conference on Parallel Processing, 1984.
C. Guerra and R. Melhem, “Synthesizing non-uniform systolic designs,”International Conference on Parallel Processing, 1986.
M.C. Chen, “A design methodology for syntehsizing parallel algorithms and architectures,”Journal of Parallel and Distributed Computing, vol. 3, 1986.
D.I. Moldovan, “On the design of algorithms for VLSI systolic arrays,”Proceedings of the IEEE, vol. 71, 1983, pp. 113–120.
H.T. Kung and Monica S. Lam, “Wafer-scale integration and two-level pipelined implementations,”Parallel and Distributed Computing, vol. 1, 1984.
S.Y. Kung, “On supercomputing with systolic/wavefront array processors,”Proceedings of the IEEE, 1984, pp. 867–884.
H.T. Kung, “Systolic algorithms for the CMU WARP processor,”Seventh International Conference on Computer Vision and Pattern Recognition, July 1984.
P.R. Cappello and K. Steiglitz, “Unifying VLSI array designs with geometric transformations,”International Conference on Parallel Processing, 1983.
J.A.B. Fortes, K.S. Fu, and B.W. Wah,Systematic approaches to the design of algorithmically specified systolic arrays, Technical Report, Department of Electrical Engineering, Purdue University, 1984.
J. Ja'Ja' and V.K. Prasanna Kumar, “Information transfer in distributed computing with applications to VLSI,”JACM, Jan. 1984.
V.K. Prasanna Kumar and Yu-Chen Tsai, “On mapping algorithms to linear and fault tolerant systolic arrays,”International Conference on Computer Design, 1986.
Author information
Authors and Affiliations
Additional information
This research was supported in part by the National Science Foundation under grant IRI-8710836 and by AFOSR under grant AFOSR-0032.
Rights and permissions
About this article
Cite this article
Prasanna Kumar, V.K., Tsai, YC. Mapping dynamic programming onto a linear systolic array. J VLSI Sign Process Syst Sign Image Video Technol 1, 335–343 (1990). https://doi.org/10.1007/BF00929926
Received:
Revised:
Published:
Issue Date:
DOI: https://doi.org/10.1007/BF00929926