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Scalable VLSI implementations for neural networks

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Abstract

This paper discusses research on scalable VLSI implementations of feed-forward and recurrent neural networks. These two families of networks are useful in a wide variety of important applications—classification tasks for feed-forward nets and optimization problems for recurrent nets—but their differences affect the way they should be built. We find that analog computation with digitally programmable weights works best for feed-forward networks, while stochastic processing takes advantage of the integrative nature of recurrent networks. We have shown early prototypes of these networks which compute at rates of 1–2 billion connections per second. These general-purpose neural building blocks can be coupled with an overall data transmission framework that is electronically reconfigured in a local manner to produce arbitrarily large, fault-tolerant networks.

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, North Carolina State University, USA

    D. van den Bout, P. Franzon, J. Paulos, T. Miller, W. Snyder, T. Nagle & W. Liu

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  1. D. van den Bout
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  2. P. Franzon
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  3. J. Paulos
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  4. T. Miller
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  5. W. Snyder
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  6. T. Nagle
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  7. W. Liu
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van den Bout, D., Franzon, P., Paulos, J. et al. Scalable VLSI implementations for neural networks. J VLSI Sign Process Syst Sign Image Video Technol 1, 367–385 (1990). https://doi.org/10.1007/BF00929928

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  • DOI: https://doi.org/10.1007/BF00929928

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