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High performance VLSI architecture for Wave Digital Filtering

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Abstract

The application of fine grain pipelining techniques in the design of high performance Wave Digital Filters (WDFs) is described. It is shown that significant increases in the sampling rate of bit parallel circuits can be achieved using most significant bit (msb) first arithmetic. A novel VLSI architecture for implementing two-port adaptor circuits is described which embodies these ideas. The circuit in question is highly regular, uses msb first arithmetic and is implemented using simple carry-save adders.

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Authors and Affiliations

  1. IFI Institute of Advanced Microelectrònics, Dept. of Electrical and Electronic Engineering, The Queen's University of Belfast, BT9 5AH, Belfast, Northern Ireland

    Rajinder Jit Singh & J. V. McCanny

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  1. Rajinder Jit Singh
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  2. J. V. McCanny
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Singh, R.J., McCanny, J.V. High performance VLSI architecture for Wave Digital Filtering. J VLSI Sign Process Syst Sign Image Video Technol 4, 269–278 (1992). https://doi.org/10.1007/BF00930640

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  • DOI: https://doi.org/10.1007/BF00930640

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