Abstract
Linear allocation functions are commonly used in mapping programs expressed as systems of recurrence equations to systolic arrays. The interconnections in a systolic array are usually required to belong to a small set ofpermissible vectors. Thus, the design space of all systolic arrays that can be derived from a given program is limited, regardless of the program being mapped. By investigating the nature of this constraint of permissible interconnections, we derive upper bounds on the number of possible systolic arrays that can be derived. These bounds are surprisingly small: there can be no more than 4 linear systolic implementations of 2-dimensional recurrences, and no more than 13 (purely systolic) planar arrays for a 3-dimensional system of recurrences. We present an efficient procedure to utilize thse bounds to generate all possible linear allocation functions for a given system of recurrences, and show how it may be used for the computer-aided design of optimal systolic arrays.
Similar content being viewed by others
References
P.R. Cappello and K. Steiglitz, “Unifying VLSI array designs with linear transformations of space-time,”Advances in Computing Research, vol. 2, 1984, pp. 23–65.
D.I. Moldovan, “On the design of algorithms for VLSI systolic arrays,”Proceedings of the IEEE, vol. 71, 1983, pp. 113–120.
R.M. Karp, R.E. Miller, and S. Winograd, “The organization of computations for uniform recurrence equations,”JACM, vol. 14, 1967, pp. 563–590.
P. Quinton, “The systematic design of systolic arrays (Ch. 9),” inAutomata Networks in Computer Science, Princeton, NJ: Princeton University Press, 1987, pp. 229–260, (preliminary versions appear as IRISA Tech Reports 193 and 216, 1983).
S. Rao,Regular Iterative Algorithms and their Implementations on Processor Arrays, Ph.D. thesis, Stanford University, Information Systems Lab., Stanford, CA, October 1985.
S.V. Rajopadhye, “Synthesizing systolic arrays with control signals from recurrence equations,”Distributed Computing, vol. 3, 1989, pp. 88–105.
V.P. Roychowdhury,Derivation, Extensions and Parallel Implementation of Regular Iterative Algorithms, Ph.D. thesis, Stanford University, Department of Electrical Engineering, Stanford, CA, December 1988.
S.Y. Kung,VLSI Array Processors, Englewood Cliffs, NJ: Prentice Hall, 1988.
P.R. Capello and S.V. Rajopadhye, “Cost measures in systolic array design,”IEEE Pacific Rim Conference on Circuits and Systems, Victoria, BC, Canada, May 1991.
W. Shang and J.A.B. Fortes, “On the optimality of linear schedules,”Journal of VLSI Signal Processing, vol. 1, 1989, pp. 209–220.
J. Wong and J-M. Delosme,Optimization of the Processor Count for Systolic Arrays, Technical Report YALEU-DCS-RR-697, Computer Science Dept., Yale University, May 1989.
S.C. Kothari, H. Oh, and E. Gannett, “Optimal designs of linear flow systolic architectures,”International Conference on Parallel Processing, St. Charles, IL, 1989.
S. Rao and T. Kailath, “What is a systolic algorithm?”SPIE Proceedings, Highly Parallel Signal Processing Architectures, Los Angeles, CA, 1986, pp. 34–48.
A. Schrijver,Theory of Integer and Linear Programming, New York: John Wiley and Sons, 1988.
X. Zhong and S.V. Rajopadhye, Quasi-linear allocation functions for efficient array design,Journal of VLSI Signal Processing, Volume 4, pp. 97–110, 1992.
Author information
Authors and Affiliations
Additional information
Supported by NSF grant MIP-8802454. Authors' email address:
Rights and permissions
About this article
Cite this article
Zhong, X., Sanjay, R. & Wong, I. Systematic generation of linear allocation functions in systolic array design. J VLSI Sign Process Syst Sign Image Video Technol 4, 279–293 (1992). https://doi.org/10.1007/BF00930641
Received:
Revised:
Published:
Issue Date:
DOI: https://doi.org/10.1007/BF00930641