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Improved CLA scheme with optimized delay

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Abstract

The delay characteristics of carry-lookahead (CLA) adders are examined with respect to a delay model that accounts for fan-in and fan-out dependencies. Though CLA structures are considered among the fastest topologies for performing addition, they have also been characterized as providing marginal speed improvement for the amount of hardware invested. This analysis shows that this inefficiency can be explained by the suboptimal nature of common CLA implementations. Simulation results show that the CLA structures in wide use can be improved by varying the block sizes and the number of levels within each adder. Examples of optimal CLA structures are given and heuristic methods for finding these structures are presented.

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Author notes

  1. Vojin G. Oklobdzija

    Present address: IBM Thomas J. Watson Research Center, 10598, Yorktown Heights, NY

Authors and Affiliations

  1. Department of Electrical Engineering and Computer Science, University of California, Berkeley

    Brian D. Lee & Vojin G. Oklobdzija

Authors
  1. Brian D. Lee
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  2. Vojin G. Oklobdzija
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Lee, B.D., Oklobdzija, V.G. Improved CLA scheme with optimized delay. J VLSI Sign Process Syst Sign Image Video Technol 3, 265–274 (1991). https://doi.org/10.1007/BF00936899

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  • DOI: https://doi.org/10.1007/BF00936899

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