Abstract
In this paper we present new algorithms for reconfiguring arrays of identical Processing Elements (PEs) in the presence of faults. In particular, we consider a well-studied reconfiguration model which consists of a rectangular array of PEs with spare columns of PEs on one side. In the presence of faulty PEs, reconfiguration is achieved by constructing alogical array using only the healthy non-spare and spare PEs. Note that one can always successfully reconfigure the array as long as the number of faulty PEs is no more than the number of spare PEs. The general objective, however, is to derive a logical array such that the geometric distances betweenlogical neighbors (i.e., PEs that are connected in the reconfigured array) are kept small. This criterion is motivated by the fact that shorter interconnects reduce the communication delays among the PEs, and also lead to less routing hardware. The problem of determining a reconfiguration that minimizes the length of the longest interconnect ishard and several researchers have presented sub-optimal algorithms that seem to have satisfactory performance. In this paper we develop anew efficient algorithm that can reconfigure any array with arbitrary patterns of faulty PEs. Furthermore we show that our algorithm performs better than most of the other algorithms developed for similar models.
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This work was supported in part by the SDIO/IST U.S. Army Research Office through Contract DAAL03-90-G-0108.
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Varvarigou, T.A., Roychowdhury, V.P. & Kailath, T. New algorithms for reconfiguring VLSI/WSI arrays. J VLSI Sign Process Syst Sign Image Video Technol 3, 329–344 (1991). https://doi.org/10.1007/BF00936905
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DOI: https://doi.org/10.1007/BF00936905