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Run-Time Reconfiguration: A method for enhancing the functional density of SRAM-based FPGAs

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Abstract

One way to further exploit the reconfigurable resources of SRAM FPGAs and increase functional density is to reconfigure them during system operation. This proces is referred to as Run-Time Reconfiguration (RTR). RTR is an approach to system implementation that divides an application or algorithm into time-exclusive operations that are implemented as separate configurations. The Run-Time Reconfiguration Artificial Neural Network (RRANN) is a proof-of-concept system that demonstrates the effectiveness of RTR for implementing neural networks. It implements the popular backpropagation training algorithm as three distinct time-exclusive FPGA configurations: feed-forward, backpropagation and update. System operation consists of sequencing through these three reconfigurationsat run-time, one configuration at a time. RRANN has been fully implemented with Xilinx FPGAs, tested and shown to increase the functional density of a network up to 500% when compared to FPGA-based implementations that do not use RTR.

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Authors and Affiliations

  1. Hewlett Packard, MS 72, 3404 East Harmony Road, 80525, Fort Collins, CO

    James G. Eldredge

  2. Reconfigurable Logic Laboratory, Department of Electrical and Computer Engineering, 459 CB, Brigham Young University, 84602, Provo, UT

    Brad L. Hutchings

Authors
  1. James G. Eldredge
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  2. Brad L. Hutchings
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Eldredge, J.G., Hutchings, B.L. Run-Time Reconfiguration: A method for enhancing the functional density of SRAM-based FPGAs. J VLSI Sign Process Syst Sign Image Video Technol 12, 67–86 (1996). https://doi.org/10.1007/BF00936947

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