Abstract
This article proposes a 7-valued logic appropriate for test generation and fault simulation, in the area of robust tests for gate delay faults, and a straightforward simulation strategy for sequential circuits. It is shown that a purely qualitative logic of robust testing is inadequate for circuits with edge-triggered flip-flops. The relation between the 7-valued logic and the similar logic proposed before by Smith, Schulz et al., and Lin and Reddy are discussed.
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References
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Hirabayashi, K. Delay fault simulation of sequential circuits. J Electron Test 4, 131–135 (1993). https://doi.org/10.1007/BF00971642
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DOI: https://doi.org/10.1007/BF00971642