Abstract
BOLD is a system that supports several test aspects of digital hardware units, such as chips, modules (boards), and systems. BOLD consists of three main components, namely a design methodology, special hardware structures, and special test languages and their associated compilers. The goal of the BOLD system is to make it feasible for an engineer to efficiently develop high quality tests for hardware units. These tests usually consist of (1) tests for faults that are internal to a unit and that are supported by one or more design-for-test or built-in self-test methodologies, and (2) interconnect tests between units. The main idea behind BOLD is to be able to easily compose tests for low level hardware units to create a test for a higher level unit.
The BOLD system employs a hierarchical design-for-test system design methodology. Each hardware unit is made testable by incorporating a test controller within its design. The controllers communicate among themselves via test busses, including, e.g., the IEEE 1149.1 boundary scan test bus.
The BOLD methodology is supported by a family of high level languages used to describe the testability aspects of chips and modules. These test descriptions are automatically synthesized into test programs. Executing a test program on a test controller at one level of the hierarchy controls the testing of hardware at lower levels of the hierarchy. The compiled test consists of test instructions and test data, gleaned automatically from the high level test program descriptions.
This article describes the test hardware configuration used, the test languages, the organization of the test descriptions, and how these descriptions are synthesized (translated) into executable test programs. The focus of this article is on the automated test program synthesis techniques employed in BOLD that can greatly reduce test program development costs.
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This work was supported by the Defense Advanced Research Projects Agency and monitored by the Federal Bureau of Investigation under Contract No. JFBI90092. The views and conclusions considered in this document are those of the authors and should not be interpreted as necessarily representing the official policies, either expressed or implied, of the Defense Advanced Research Projects Agency or the U.S. Government.
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Lien, JC., Breuer, M.A. Test program synthesis for modules and chips having boundary scan. J Electron Test 4, 159–180 (1993). https://doi.org/10.1007/BF00971645
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DOI: https://doi.org/10.1007/BF00971645