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An approach to sequential circuit diagnosis based on formal verification techniques

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Abstract

This article deals with the generation of exact diagnostic trees for real-size synchronous sequential circuits. Starting from existing detection-oriented test patterns, a modified fault simulator is used for assessing their diagnostic power, which, in general, is not satisfactory. A diagnostic procedure for improving it is described that successfully exploits symbolic FSM equivalence proof algorithms. In order to resort to costly techniques, such as product machine traversal, only when really needed, special checks are performed to verify combinational identity and identity on reachable states. As all faults are attributed to theirequivalence class, a complete and exact diagnostic tree can be built. Experimental results on ISCAS'89 circuits show the feasibility of the approach and support the claim that, for the first time, diagnosing real-world synchronous sequential circuits has become feasible.

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Authors and Affiliations

  1. Dipartimento di Automatica e Informatica, Politecnico di Torino, Corso Duca degli Abruzzi 24, I-10129, Turin, Italy

    G. Cabodi, P. Camurati, F. Corno, P. Prinetto & M. Sonza Reorda

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  1. G. Cabodi
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  2. P. Camurati
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  3. F. Corno
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  4. P. Prinetto
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  5. M. Sonza Reorda
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Cabodi, G., Camurati, P., Corno, F. et al. An approach to sequential circuit diagnosis based on formal verification techniques. J Electron Test 4, 11–17 (1993). https://doi.org/10.1007/BF00971936

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  • DOI: https://doi.org/10.1007/BF00971936

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