Abstract
A Booth multiplier is the most widely used type of multiplier. In this article, the testability issues involved in its design are discussed. In contrast to previous work, the fault model includes not only node stuck-at faults, but also transistor stuck-open and stuck-close faults. Moreover, as a result of adopting a hierarchical testability approach, the designed Booth multiplier turns out to be fully C-testable. To achieve this C-testability, only three additional controllable inputs are required, which results in a negligible area and delay overhead.
Similar content being viewed by others
Explore related subjects
Discover the latest articles and news from researchers in related subjects, suggested using machine learning.References
M.S. Abadir and M.A. Breuer, “Test schedules for VLSI circuits having built-in test hardware,”IEEE Trans. Comput., pp. 361–367, April 1985.
P. Agrawal, “Test generation at MOS level,” inProc. Int. Conf. on Computers, Systems and Signal Processing, Bangalore, India, Dec. 1984.
F. Beenker, K. van Eerdewijk, R. Gerritsen, F. Peacock, and M. van der Star, “Macro testing: unifying IC and board test,”IEEE Design & Test of Comput., vol. 3, pp. 26–32, Dec. 1986.
A.D. Booth, “A signed binary multiplication technique,”A.J. Mech. Appl. Math. 4, pp. 260–264, April 1951.
F. Catthoor, J. van Sas, L. Inzé, and H. De Man, “A testability strategy for multi-processor architecture,IEEE Design & Test of Comput., vol. 6, pp. 18–34, April 1989.
S. Chakravarty and S.S Ravi, “Computing optimal test sequences from complete test sets for stuck-open faults in CMOS circuits,”IEEE Trans. on Comput., vol. 9, pp. 329–331, March 1990.
A. Chatterjee and J.A. Abraham, “Test generation for arithmetic units by graph labeling,” inProc. Int. Symp. Fault-Tolerant Comput., Pittsburgh, PA, pp. 284–289, July 1987.
H. De Man, F. Catthoor, G. Goossens, J. Vanhoof, J. Van Meerbergen, and J. Huisken, “Architecture driven synthesis techniques for mapping digital signal processing algorithms into silicon,”Special Issue of the Proceedings of the IEEE devoted to CAD, vol. 78, pp. 319–336, Feb. 1990.
H. Elhuni, A. Vergis, and L. Kinney, “C-testability of two-dimensional iterative arrays,”IEEE Trans. CAD/ICAS, vol. 5, pp. 573–581, Oct. 1986.
A.D. Friedman, “Easily testable iterative systems,”IEEE Trans. Comput., vol. C-22, pp. 1061–1064, Dec. 1973.
S.K. Jain and V.D. Agrawal, “Test generation for MOS circuits using D-algorithm,” inProc. Design Automation Conf., Miami, Beach, FL, pp. 64–70, June 1983.
T-W. Ku and M. Soma, “Minimal overhead modification of iterative logic arrays for C-testability,” inProc. IEEE Int. Test Conf. 1990, pp. 964–969, Sept. 1990.
J. Pineda de Gyvez, “LASER: A Layout Sensitive Explorer, Report and User's Manual,” Eindhoven University of Technology, EUT Report 89-E-216, ISBN 90-6144-216-8, March 1989.
LOFSCATE user's manual version 7.1, LAMM, March 1989.
Y. Malaiya, A. Jayasumana, and R. Rajsuman, “A detailed examination of bridging faults,” inProc. Int'l. Conf. Computer Design, pp. 78–81, Oct. 1986.
W. Maly, “Modeling of lithography related yield losses for CAD of VLSI circuits,”IEEE Trans. CAD/ICAS, vol. CAD-4, pp. 166–177, July 1985.
17.A.V. Oppenheim (ed.),Applications of Digital Signal Processing, Prentice Hall, Englewood Cliffs, NJ, 1978.
R. Parthasarathy and S. Reddy, “A testable design of iterative logic arrays,”IEEE Trans. Comput., vol. C-30, pp. 833–841, Nov. 1981.
J.P. Roth, “Diagnosis of automata failures: A calculus and a method,”IBM J. Res. Dev. vol. 10, pp. 278–281, 1966.
L.P. Rubinfield, “A proof of the modified Booth algorithm for multiplication,”IEEE Trans. Comput., vol. C-24, pp. 1014–1015, Oct. 1975.
J.P. Shen and F.J. Ferguson, “The design of easily-testable VLSI array multipliers,”IEEE Trans. Comput., vol. C-33, pp. 554–560, June 1984.
R. Stans, “The testability of a modified Booth multiplier,” inProc. of 1st European Test Conf. ETC'89, pp. 286–293, April 1989.
T.M. Storey and W. Maly, “CMOS bridging fault detection,” inProc. IEEE Int. Test Conf. 1990, pp. 842–851, Sept. 1990.
A. Takach and N. Jha, “Easily testable gate-level and DCVS multipliers,”IEEE Trans. CAD/ICAS, vol. 10, pp. 932–942, July 1991.
J. van Sas, F. Catthoor, and H. De Man, “Test algorithms for double-buffered random access and pointer addressed memories,”IEEE Design & Test of Comput., pp. 34–44, June 1993.
R.L. Wadsack, “FAult modeling and logic simulation of CMOS and MOS integrated circuits,”The Bell Tech. J., vol. 57, pp. 1449–1474, May–June 1978.
Author information
Authors and Affiliations
Additional information
Currently with Alcatel Bell Telephone.
Rights and permissions
About this article
Cite this article
Van Sas, J., Nowé, C., Pollet, D. et al. Design of a C-testable booth multiplier using a realistic fault model. J Electron Test 5, 29–41 (1994). https://doi.org/10.1007/BF00971961
Received:
Revised:
Issue Date:
DOI: https://doi.org/10.1007/BF00971961