Abstract
This article presents new approaches for testing VLSI array architectures used in the computation of the complexN-point Fast Fourier Transform. Initially, an unrestricted single cell-level fault model is considered. The first proposed approach is based on a process whose complexity is independent (or C- as constant) of the number of cells in the FFT architecture. This is accomplished by showing a topological equivalence between the FFT array and a linear (one-dimensional) array. The process of fault location is also analyzed. The second proposed method is based on a testing process whose complexity is linear with respect to the number of stages (columns) of the FFT array. A component-level fault model is also proposed and analyzed. The implications of this model on the C-testability process are fully described.
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This research is supported by grants from NSF and NSERC.
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Feng, C., Muzio, J.C. & Lombardi, F. On the testability of array structures for FFT computation. J Electron Test 4, 215–224 (1993). https://doi.org/10.1007/BF00971971
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DOI: https://doi.org/10.1007/BF00971971