Abstract
We present a fast fault simulation algorithm for combinational circuits which combines parallel pattern evaluation and critical path tracing. When the number of faults is large, our algorithm exploits the full advantages of critical path tracing. As fault dropping progresses, the overhead for critical path tracing surpasses its advantages. On the other hand, the efficiency of Parallel Pattern Single Fault Propagation (PPSFP) increases rapidly since relatively few undetected faults remain, and they tend to be inactive. To avoid the overhead of critical path tracing and achieve the advantages of PPSFP, dynamic update of node classes is used to produce a smooth transition from critical path tracing to PPSFP. By using this approach, we get high performance for both small and large numbers of test patterns. Also, preprocessing related to structure analysis is avoided while achieving almost all of its advantages.
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References
S.J. Hong, “Fault simulation strategy for combinational logic networks,”Dig. Int. Symp. of Fault-Tolerant Computing, pp. 96–99, June 1978.
D. Armstrong, “A deductive method for simulating faults in logic circuits,”IEEE Trans. on Computers, Vol. C21, pp. 464–471, May 1972.
E. Ulrich and T. Baker, “The concurrent simulation of nearly identical digital networks,”Proc. Design Automation Conf., pp. 145–150, June 1973.
M. Abramovici, P. Menon, and D. Miller, “Critical path tracing—an alternative to fault simulation,”Proc. Design Automation Conf., pp. 214–220, June 1983.
J. Waicukauski, E. Eichelberger, D. Forlenza, E. Lindbloom, and T. McCarthy, “A statistical calculation of fault detection probabilities by fast fault simulation,”Proc. Int. Test Conf., pp. 779–784, December 1985.
K. Antreich and M. Schulz, “Accelerated fault simulation and fault grading in combinational circuits,”IEEE Trans. on Computer-Aided Design, vol. CAD-6, pp. 704–712, September 1987.
O. Song and P. Menon, “Parallel pattern fault simulation based on stem faults in combinational circuits,”Proc. Int. Test Conf., pp. 706–711, September 1990.
F. Maamari and J. Rajski, “A method of fault simulation based on stem regions,”IEEE Trans. on Computer-Aided Design, vol. 9, pp. 212–220, February 1990.
F. Maamari and J. Rajski, “The dynamic reduction of fault simulation,”Proc. Int. Test Conf., pp. 801–808, September 1990.
B. Underwood and J. Ferguson, “The parallel-test-detect fault simulation algorithm,”Proc. Int. Test Conf., pp. 712–717, August 1989.
J. Roth, W. Bouricius, and P. Schneider, “Programmed algorithms to compute tests to detect and distinguish between failures in logic circuits,”IEEE Trans. on Computers, vol. EC-16, pp. 567–580, October 1967.
S.P. Smith, “An enhanced high performance combinational fault simulator using two-way parallelism,”Int. Conf. on Computer Design, pp. 294–297, October 1989.
H. Lee and D. Ha, “An efficient, forward fault simulation algorithm based on the parallel pattern single fault propagation,”Proc. Int. Test Conf., pp. 946–955, September 1991.
D. Wang, “An algorithm for the generation of test sets for combinational logic networks,”IEEE Trans. on Computers, vol. C-24, pp. 742–746, July 1975.
F. Brglez and H. Fujiwara, “A neutral netlist of 10 combinational benchmark circuits and a target translator in Fortran,”Proc. Int. Symp. on Circuits and Systems, pp. 663–698, June 1985.
F. Brglez, D. Bryan, and K. Kozminski, “Combinational profiles of sequential benchmark circuits,”Proc. Int. Symp. on Circuits and Systems, pp. 1929–1934, May 1989.
I. Pomeranz, L. Reddy, and S. Reddy, “COMPACTEST: a method to generate compact test sets for combinational circuits,”Proc. Int. Test Conf., pp. 194–203, September 1991.
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This work was supported in part by National Science Foundation grant MIP-9003292.
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So, B.S., Kime, C.R. A fault simulation method: Parallel pattern critical path tracing. J Electron Test 4, 255–265 (1993). https://doi.org/10.1007/BF00971974
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DOI: https://doi.org/10.1007/BF00971974