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Economics of “design for test” to remain competitive in the 90s

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Abstract

This article emphasizes the criticality of maximizing “value adders” and minimizing the costs of “design for test” (DFT) in order to remain competitive in ASIC manufacturing in the 90s.

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References

  1. C. Maunder, “Boundary Scan: An End-of-Term Report”,IEEE Design & Test of Computers, June 1992, pp. 82–85.

  2. LSI Logic, “Chip-Level Full-Scan Design Methodology”, Jan. 1992.

  3. Solution Strategies, Testable ASICs, pp. 3–8.

  4. T.W. Williams and N.C. Brown, “Defect Level as a Function of Fault Coverage”,IEEE Trans. Computers, vol. C-30, pp. 987–988, Dec. 1981.

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  5. E.J. McCluskey and F. Buelow, “IC Quality and Test Transparency”,Proceedings of the IEEE CS Press, 1988, pp. 295–301.

  6. F. Zarrinfar, “The Four Major Forces That Drive ASIC Test-ability”,Proceedings of the 1993 DESIGN & TEST EXPO.

  7. Prime Data, “Addressing the Integration of Design & Test”, Feb. 1993.

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Zarrinfar, F. Economics of “design for test” to remain competitive in the 90s. J Electron Test 5, 171–177 (1994). https://doi.org/10.1007/BF00972077

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