Abstract
In this article, scan design for testability (DFT) methods are categorized based on the percentage of storage elements made scannable. The non-scan element state retention problem that occurs in partial scan design methods, in which not all of the storage elements are implemented as scan elements, is discussed. Solutions to this problem are described and the overheads associated with them are discussed. An economic model that allows the costs of a range of scan methods that differ in the percentage of storage elements made scannable to be compared with each other is presented. It is shown that, for systems produced in low volumes, the adoption of full scan DFT can be more cost-effective than partial scan DFT when life-cycle costs are considered if it results in significant reductions in the time taken to get the product to market.
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Varma, P., Gheewala, T. The economics of scan-path design for testability. J Electron Test 5, 179–193 (1994). https://doi.org/10.1007/BF00972078
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DOI: https://doi.org/10.1007/BF00972078