Abstract
In this article we propose efficient scan path and BIST schemes for RAMs. Tools for automatic generation of these schemes have been implemented. They reduce the design effort and thus allow the designer to select the more appropriate scheme with respect to various constraints.
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References
S.M. Thatte and J.A. Abraham, “Testing of Semiconductor Random Access Memories”Proc. IEEE 7th Intern. Conf. on Fault-Tolerant Comput. (FTCS), USA, 1977, pp. 81–87.
A.J. Van de Goor and C.A. Verruijt, “An Overview of Deterministic Functional RAM Chip Testing,”ACM Computing Surveys, vol. 22, no. 1, March 1990, pp. 5–33.
M. Marinescu, “Simple and Efficient Algorithms for Functional RAM Testing,”Proc. IEEE Intern. Test Conf. (ITC), USA, Nov. 1982, pp. 236–239.
D.S. Suk, and S.M. Reddy, “A March Test for Functional Faults in Semiconductor Random Access Memories,”IEEE Trans. on Comput. vol. C-30, no. 12, Dec. 1981, pp. 982–985.
C.V. Alves, M. Nicolaidis, P. Lestrat, and B. Courtois, “Built-in Self-Test for Multi-Port Rams,”Proc. IEEE Intern. Conf. on Computer-Aided Design (ICCAD), Santa Clara, USA, Nov. 1991, pp. 248–251.
M. Nicolaidis, “An Efficient Built-In Self-Test for Functional Test of Embedded RAMs,”Proc. IEEE 15th International Symp. on Fault-Tolerant Comput., Ann Arbor, USA, June 1985, pp. 118–123.
M. Nicolaidis, O. Kebichi and V.C. Alves, “Trade-Offs in Scan Path and BIST Implementation for RAMs,” TIMA Research Report No. RR 93. 2-I-Sept. 1993.
O. Kebichi and M. Nicolaidis, “A Tool for Automatic Generation of BISTed RAMs,”Proc. IEEE Intern. Conf. on Computer Design, (ICCD), Cambridge, USA, Oct. 1992, pp. 570–576.
M. Nicolaidis, “Transparent Testing of Integrated Circuit,” Greek Patent 920100088 5/3/92, Institute of Industrial Property, Athens, Greece, March 1992.
M. Nicolaidis, V.C. Alves, and O. Kebichi, “Trade-Offs in Scan Path and BIST Implementation for RAMs,”Proc. IEEE European Test Conf. (ETC), Rotterdam, April 1993, pp. 169–178.
H. Maeno, K. Nii, S. Sakayanagi, and S. Kato, “LSSD Compatible and Concurrently Testable RAM,”Proc. IEEE Intern. Test Conf. (ITC), Baltimore USA, Sept. 1992, pp. 608–614.
P. Bardel, W. McAnnoy, J. Savir,Built-In Test for VLSI: Pseudorandam Techniques, Wiley Interscience, New York, USA, 1987.
M. Nicolaidis, “Transparent BIST for RAMs,”Proc. IEEE Intern. Test Conf. (ITC), Baltimore USA, Sept. 1992, pp. 598–607.
W.C. Carter, and P.R. Schneider, “Design of Dynamically Checked Computers,”Proc. IFIP 68 Cong., Amsterdam, 1968, pp. 878–883.
V. Zorian and A. Ivanov, “EEODM: An Effective BIST Scheme for ROMs,”Proc. IEEE Intern. Test Conf. (ITC), Washington DC, USA, Sept. 1990, pp. 871–879.
P. Varma, A.P. Ambler, and K. Baker, “An Analysis of the Economics of Self-Test,”Proc. IEEE Intern. Test Conf., USA, Oct. 1984, pp. 20–30.
I.D. Dear and A.P. Ambler, “Predicting Cost and Quality Improvement as Result of Test Strategy Planning,”IFIP Workshop on fast prototyping of VLSI, March 1987, pp. 225–237.
A.P. Ambler, M. Paraskeva, D.F. Burrows, W.L. Knight and I.D. Dear, “Economically Viable Automatic Insertion of Self-Test Features for Custom VLSI,”IEEE Intern. Test Conf. (ITC), Sept. 1986, pp. 232–243.
R.E. Huston, “An Analysis of ATE Testing Costs,”Proc. IEEE Intern. Test Conf. (ITC), Oct. 1983, pp. 396–411.
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Nicolaidis, M., Kebichi, O. & Alves, V.C. Trade-offs in scan path and BIST implementations for RAMs. J Electron Test 5, 273–283 (1994). https://doi.org/10.1007/BF00972087
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DOI: https://doi.org/10.1007/BF00972087