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Self-test of sequential circuits with deterministic test pattern sequences

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Abstract

This article describes a new approach for synthesizing a cost-efficient self-test hardware for a given set of deterministic test pattern sequences. To minimize the test hardware effort instead of all the test sequences, only a very small subset will be selected such that a simple generation of all necessary test sequences will be ensured. This procedure drastically decreases the storage requirements (about 80%) and therefore distinctly reduces the necessary test hardware overhead. Experimental results on the ISCAS-S-benchmarks emphasize the efficiency of our approach.

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Authors and Affiliations

  1. Forschungszentrum Informatik (FZI), Haid-und-Neu-Strasse 10-14, 76131, Karlsruhe

    Arno Kunzmann & Frank Boehland

Authors
  1. Arno Kunzmann
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  2. Frank Boehland
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This work is supported by the ESPRIT project 6855 (LINK).

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Kunzmann, A., Boehland, F. Self-test of sequential circuits with deterministic test pattern sequences. J Electron Test 5, 307–312 (1994). https://doi.org/10.1007/BF00972090

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  • DOI: https://doi.org/10.1007/BF00972090

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