Abstract
Research in the areas of analog circuit fault simulation and test generation has not achieved the same degree of success as its digital counterpart owing to the difficulty in modeling the more complex analog behavior. This article presents a novel approach to this problem by mapping the good and faulty circuits to thediscrete Z-domain. An efficient fault simulation is then performed on this discretized circuit for the given input test wave form. This simulator provides an order of magnitude speedup over traditional circuit simulators. An efficient fault simulator and the formulation of analog fault models opens up the ground for analog automatic test generation.
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Nagi, N., Chatterjee, A. & Abraham, J.A. Fault simulation of linear analog circuits. J Electron Test 4, 345–360 (1993). https://doi.org/10.1007/BF00972159
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DOI: https://doi.org/10.1007/BF00972159