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Effective march algorithms for testing single-order addressed memories

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Abstract

Today's commonly used macro generators provide for read/write memories of type SRAM, Register File, Multi-Port RAM, Single-Order Addressed Memory (e.g. FIFO), CAM (Content Addressable Memory), etc. In addition to automatically generating the required momory, the appropriate test, which may be applied externally or internally as a BIST, has to be determined.

Current literature provides tests for most memory types; however, tests for single-order addressed (SOA) memories, whereby the address can only change in one direction (e.g. from address 0 ton-1) have not been published yet. SOA memories are used in FIFOs and in applications where the BIST area overhead and/or speed penalty for normal (dual) order addressing are not acceptable.

This article illustrates the testing problems and presents a family of march algorithms optimized for testing SOA memories.

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Van De Goor, A.J., Zorian, Y. Effective march algorithms for testing single-order addressed memories. J Electron Test 5, 337–345 (1994). https://doi.org/10.1007/BF00972518

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  • DOI: https://doi.org/10.1007/BF00972518

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