Abstract
Signature analyzers are very efficient output response compactors for BIST design. The only limitation of signature analysis is the fault coverage reduction (aliasing) due to the information loss inherent to any data compaction. In this article, in order to increase the effectiveness of ROM BIST, we take advantage from the simplicity of the error patterns generated by ROMs and we show that aliasing free signature analysis can be achieved in ROM BIST.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
E.J. McCluskey,Logic design principles, Prentice Hall, Englewood Cliffs, New Jersey 07632, 1986.
Y. Zorian and A. Ivanov “EEODM: An Effective BIST scheme for ROMs,”Proc. IEEE Int. Test Conf., Washington, DC, pp. 871–879, September 1990.
P.H. Bardell, W.C. McAnney, and J. Savir,Built-In Self-Test for VLSI. Pseudorandom Techniques, John Wiley & Sons, 1987.
J. Savir, “The Bidirectional Double Latch,”IEEE Trans. Comp., vol. C-35, No. 1, pp. 440–445, January 1986.
I. Pomeranz, S.M. Reddy, and R. Tangirala, “On Achieving Zero Aliasing for Modeled Faults,”Proc. European Conference on Design Automation, Brussels, Belgium, pp. 291–299, March 1992.
Author information
Authors and Affiliations
Additional information
This work was performed when the author was on leave from Minsk Radio Engineering Institute, Computer Department, Belorus.
Rights and permissions
About this article
Cite this article
Kebichi, O., Yarmolik, V.N. & Nicolaidis, M. Zero aliasing ROM BIST. J Electron Test 5, 377–388 (1994). https://doi.org/10.1007/BF00972521
Received:
Revised:
Issue Date:
DOI: https://doi.org/10.1007/BF00972521