Abstract
If the statistics available from various process steps involved in the fabrication of large-scale integrated logic circuit chips indicate that the computed probability of each circuit path operating properly is greater than 1/2, then a reliable screening test procedure can be devised. A reliable reference standard from untested chips, or modules, can be constructed, and such a standard reference can be used in all test procedures in which circuit testing is based on comparison.
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References
S. Winograd and J. D. Cowan,Reliable Computation in the Presence of Noise (MIT Press, Cambridge, Mass., 1963).
E. Parzen,Modern Probability Theory and Its Applications (John Wiley & Sons, New York, 1962).
Tables of the Binomial Probability Distribution, Applied Mathematics Series 6 (National Bureau of Standards, Washington, D.C., 1950).
F. D. Erwin and J. F. McKevitt, “Characters Universal Architecture,”AFIPS Conference Proceedings, Vol. 35 (1969).
I. T. Ho, G. A. Maley, and R. Waxman, “Latent Image Memory,” ISSCC, University of Pennsylvania (1971).
W. Luciw, “Can a user test LSI Microprocessor Effectively,” IEEE Semiconductor test Symposium (October 1975).
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Singh, S., Pal Singh, V. A probabilistic approach for testing large-scale integrated circuits. International Journal of Computer and Information Sciences 7, 283–294 (1978). https://doi.org/10.1007/BF00991634
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DOI: https://doi.org/10.1007/BF00991634