Abstract
Testability analysis of neural architectures can be performed at a very high abstraction level on the computational paradigm. In this paper, we consider the case of feed-forward multi-layered neural networks. We introduce a behavioral error model which allows good mapping of the physical faults in widely different implementations. Conditions for error controllability, observability and global testability are analytically derived; their purpose is that of verifying whether it is possible to excite all modeled errors and to propagate the error's effects to the primary outputs (actual test vectors being then technological-dependent). Mapping of physical faults onto behavioral errors is performed for some representative, architectures.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
J. Beichter, U. Ramacher, and H. Klar, ”VLSI design of a neural signal processor,”Proc. IFIP Workshop on Silicon Architectures for Neural Networks, St. Paul de Vence, France, pp. 245–260, 1990.
C. Lehmann and F. Blayo, “A VLSI implementation of a generic systolic synaptic building block for neural networks,”Proc. Int'l Workshop on VLSI for artificial intelligence and neural networks, Oxford, UK, pp. G7:1–12, 1990.
F. Distante, M. Sami, R. Stefanelli, and G. Storti-Gajani, “Fault tolerant characteristics of the linear array architecture for WSI implementation of neural nets,”Proc. IEEE International Conference on WSI San Francisco, CA, pp. 113–120, 1991.
P.Y. Alla, J. Ouali, G. Saucier, L. Masse-Navette, and J. Trilhe, “Silicon compilation of neuro-ASICs supported by a distributed and synchronous neural network architecture,”Proc. 2nd Int'l Conf. on Microelectronics for Neural Networks, Munich, Germany, pp. 341–346, 1991.
C. Mead,Analog, VLSI and Neural Systems, Addison-Wesley Publishing Co., Reading, MA, 1989.
P.Y. Alla, G. Saucier, S. Knerr, and L. Personnaz, “Design and implementation of a dedicated neural network for handwritten digit recognition,”Proc. IFIP Workshop on Silicon Architectures for Neural Nets, St. Paul de Vence, France, pp. 261–270, 1990.
M. Yasunaga et al., “Design, fabrication and evaluation of a 5-inch wafer scale neural network LSI composed of 576 digital neurons,”Proc. IJCNN 1990, San Diego, CA, pp. 1350–1354, 1990.
P.Y. Alla, G. Dreyfus, J.D. Gascuel, A. Johannet, L. Personnaz, J. Roman, and M. Weinfeld, “Silicon integration of learning algorithm and other auto-adaptive properties in a digital feedback neural network,”Proc. IEEE/ITG Workshop on Microelectronics for Neural Networks, Dortmund, Germany, pp. 40–46, 1990.
S.Y. Kung, “Parallel architectures for artificial neural nets,”Proc. Systolic Arrays 1988, San Diego, CA, pp. 163–174, 1988.
C.H. Chen, C. Wu, and D.G. Saab, “BETA: behavioral testability analysis,”Proc. ICCAD, Santa Clara, CA, pp. 202–205, 1991.
M. Bombana, G. Buonanno, P. Cavallro, D. Seiuto, and G. Zaza, “A multi-level testability assistant for VLSI design,”Proc. EuroDAC 92, Hamburg, Germany, pp. 258–263, 1992.
A. Antola, M. Sami, and D. Sciuto, “High-level design of algorithm-driven architectures: the testability and diagnosability issue,”Proc. Int'l Conf. on Wafer-Scale Integration, San Francisco, CA, pp. 271–280, 1992.
D. Bhattacharya and J.P. Hayes, “A Hierarchical Test Generation Methodology for Digital Circuits,”Journal of Electronic Testing: Theory and Applications, Vol. 1, No. 2, pp. 103–124, May 1990.
J. Hertz, A. Krog, and R.G. Palmer,Introduction to the Theory of Neural Computation, Addison-Wesley, Redwood City, CA, 1991.
C.H. Chen and P.R. Menon, “An approach to functional level testability analysis,”Proc. ITC, pp. 188–191, 1989.
M. Stevenson, R. Winter, and B. Widrow, “Sensitivity of feedforward neural networks to weight errors,”IEEE Trans. Neural Networks, Vol. 1, No. 1, pp. 71–80, March 1990.
C. Alippi, V. Piuri, and M. Sami, “The issue of error sensitivity in neural networks,”Proc. IEEE Conference on Massively Parallel Computing Systems, Ischia Italy, pp. 464–476, May 1994.
D.E. Rumelhart and J.L. McClelland, itors,Parallel Distributed Processing: Explorations in the Microstructure of Cognition, Vol. 1, MIT Press, Cambridge, MA, 1986.
D. Zhang, G.A. Jullien, W.C. Miller, and E. Swartzlander, “Arithmetic for Digital Neural Networks,”Proc. 10th IEEE Symp. Computer Arithmetics, Grenoble, France, pp. 78–83, 1991.
F. Distante, M. Sami, R. Stefanelli, and G. Storti-Gajani, “A compact and fast silicon implementation for layered neural nets.,”Proc. Int'l Workshop on VLSI for artificial intelligence and neural networks, Oxford, U.K., pp G9:1–11, 1990.
F. Distante, M. Sami, R. Stefanelli, and G. Storti-Gajani, “Mapping neural nets onto a massively parallel architecture. a defect-tolerance solution,”IEEE Proceedings, Vol. 79, No. 4, pp. 444–460, April 1991.
M. Annaratone and R. Stefanelli, “A multiplier with multiple error correction capability,”Proc. ARITH-6 pp. 44–51, 1983.
Author information
Authors and Affiliations
Rights and permissions
About this article
Cite this article
Piuri, V., Sami, M. & Sciuto, D. Testability of artificial neural networks: A behavioral approach. J Electron Test 6, 179–190 (1995). https://doi.org/10.1007/BF00993085
Received:
Revised:
Accepted:
Issue Date:
DOI: https://doi.org/10.1007/BF00993085