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Evaluating the safety of self-checking circuits

  • Self-test and Self-checking Circuits
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Abstract

In this paper, we consider the evaluation of the safety of a self-checking circuit with combinational logic. Since the circuit is tested under normal operation, it may stay in different states such as a perfect state in which any erroneous output can be detected, unstable states in which an erroneous output may be detected or may not, a safe-state when the erroneous output has been caught, and a fail-state because the erroneous output is undetected, as time goes on. Consequently, we propose a fail-safe evaluation, using a Markov model to describe the state transitions and predicate the probability of the circuit not being in the fail-state.

We include a comparison with existing evaluation methods, the proposed approach being more practical because it estimates the safety of the circuit, which is reducing as time goes on, instead of giving a constant probability measure.

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Authors and Affiliations

  1. Department of Computer Science, University of Victoria, V8W 3P6, Victoria, B.C., Canada

    Shujian Zhang & Jon C. Muzio

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  1. Shujian Zhang
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  2. Jon C. Muzio
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Additional information

This work was supported in part by Research Grant No. 5711 from the Natural Sciences and Engineering Research Council of Canada and by an equipment loan from the Canadian Microelectronics Corporation.

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Zhang, S., Muzio, J.C. Evaluating the safety of self-checking circuits. J Electron Test 6, 243–253 (1995). https://doi.org/10.1007/BF00993090

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  • DOI: https://doi.org/10.1007/BF00993090

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